📄 testfreq.tan.qmsg
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/testfreq/Block1.bdf" { { 160 -104 64 176 "clk" "" } } } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" { } { { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/testfreq/Block1.bdf" { { 264 -88 80 280 "clock" "" } } } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "testfreq:inst3\|comb~0 " "Info: Detected gated clock \"testfreq:inst3\|comb~0\" as buffer" { } { { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "testfreq:inst3\|comb~0" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "testfreq:inst3\|clr " "Info: Detected ripple clock \"testfreq:inst3\|clr\" as buffer" { } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 11 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "testfreq:inst3\|clr" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "testfreq:inst3\|clk1 " "Info: Detected ripple clock \"testfreq:inst3\|clk1\" as buffer" { } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 11 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "testfreq:inst3\|clk1" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "LED:inst1\|clk1 " "Info: Detected ripple clock \"LED:inst1\|clk1\" as buffer" { } { { "LED.vhd" "" { Text "D:/Project/Quartus II/testfreq/LED.vhd" 14 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "LED:inst1\|clk1" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register testfreq:inst3\|freq1\[0\] register testfreq:inst3\|freq\[0\] 74.24 MHz 13.47 ns Internal " "Info: Clock \"clk\" has Internal fmax of 74.24 MHz between source register \"testfreq:inst3\|freq1\[0\]\" and destination register \"testfreq:inst3\|freq\[0\]\" (period= 13.47 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.148 ns + Longest register register " "Info: + Longest register to register delay is 0.148 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns testfreq:inst3\|freq1\[0\] 1 REG LC_X25_Y10_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y10_N8; Fanout = 1; REG Node = 'testfreq:inst3\|freq1\[0\]'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { testfreq:inst3|freq1[0] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.148 ns) 0.148 ns testfreq:inst3\|freq\[0\] 2 REG LC_X25_Y10_N8 2 " "Info: 2: + IC(0.000 ns) + CELL(0.148 ns) = 0.148 ns; Loc. = LC_X25_Y10_N8; Fanout = 2; REG Node = 'testfreq:inst3\|freq\[0\]'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.148 ns" { testfreq:inst3|freq1[0] testfreq:inst3|freq[0] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 47 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.148 ns ( 100.00 % ) " "Info: Total cell delay = 0.148 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.148 ns" { testfreq:inst3|freq1[0] testfreq:inst3|freq[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "0.148 ns" { testfreq:inst3|freq1[0] testfreq:inst3|freq[0] } { 0.000ns 0.000ns } { 0.000ns 0.148ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.550 ns - Smallest " "Info: - Smallest clock skew is -6.550 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.787 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 157 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 157; CLK Node = 'clk'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/testfreq/Block1.bdf" { { 160 -104 64 176 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.607 ns) + CELL(0.711 ns) 2.787 ns testfreq:inst3\|freq\[0\] 2 REG LC_X25_Y10_N8 2 " "Info: 2: + IC(0.607 ns) + CELL(0.711 ns) = 2.787 ns; Loc. = LC_X25_Y10_N8; Fanout = 2; REG Node = 'testfreq:inst3\|freq\[0\]'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.318 ns" { clk testfreq:inst3|freq[0] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 47 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.22 % ) " "Info: Total cell delay = 2.180 ns ( 78.22 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.607 ns ( 21.78 % ) " "Info: Total interconnect delay = 0.607 ns ( 21.78 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.787 ns" { clk testfreq:inst3|freq[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.787 ns" { clk clk~out0 testfreq:inst3|freq[0] } { 0.000ns 0.000ns 0.607ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.337 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 9.337 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 157 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 157; CLK Node = 'clk'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/testfreq/Block1.bdf" { { 160 -104 64 176 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.935 ns) 3.009 ns testfreq:inst3\|clr 2 REG LC_X17_Y6_N3 21 " "Info: 2: + IC(0.605 ns) + CELL(0.935 ns) = 3.009 ns; Loc. = LC_X17_Y6_N3; Fanout = 21; REG Node = 'testfreq:inst3\|clr'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.540 ns" { clk testfreq:inst3|clr } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.899 ns) + CELL(0.292 ns) 5.200 ns testfreq:inst3\|comb~0 3 COMB LC_X8_Y6_N5 20 " "Info: 3: + IC(1.899 ns) + CELL(0.292 ns) = 5.200 ns; Loc. = LC_X8_Y6_N5; Fanout = 20; COMB Node = 'testfreq:inst3\|comb~0'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.191 ns" { testfreq:inst3|clr testfreq:inst3|comb~0 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.023 ns) + CELL(0.114 ns) 9.337 ns testfreq:inst3\|freq1\[0\] 4 REG LC_X25_Y10_N8 1 " "Info: 4: + IC(4.023 ns) + CELL(0.114 ns) = 9.337 ns; Loc. = LC_X25_Y10_N8; Fanout = 1; REG Node = 'testfreq:inst3\|freq1\[0\]'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.137 ns" { testfreq:inst3|comb~0 testfreq:inst3|freq1[0] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.810 ns ( 30.10 % ) " "Info: Total cell delay = 2.810 ns ( 30.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.527 ns ( 69.90 % ) " "Info: Total interconnect delay = 6.527 ns ( 69.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.337 ns" { clk testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "9.337 ns" { clk clk~out0 testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[0] } { 0.000ns 0.000ns 0.605ns 1.899ns 4.023ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.114ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.787 ns" { clk testfreq:inst3|freq[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.787 ns" { clk clk~out0 testfreq:inst3|freq[0] } { 0.000ns 0.000ns 0.607ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.337 ns" { clk testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "9.337 ns" { clk clk~out0 testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[0] } { 0.000ns 0.000ns 0.605ns 1.899ns 4.023ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.114ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" { } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 35 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 47 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 35 -1 0 } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 47 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.148 ns" { testfreq:inst3|freq1[0] testfreq:inst3|freq[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "0.148 ns" { testfreq:inst3|freq1[0] testfreq:inst3|freq[0] } { 0.000ns 0.000ns } { 0.000ns 0.148ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.787 ns" { clk testfreq:inst3|freq[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.787 ns" { clk clk~out0 testfreq:inst3|freq[0] } { 0.000ns 0.000ns 0.607ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.337 ns" { clk testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "9.337 ns" { clk clk~out0 testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[0] } { 0.000ns 0.000ns 0.605ns 1.899ns 4.023ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.114ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock register register testfreq:inst3\|count2\[1\] testfreq:inst3\|count2\[19\] 275.03 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 275.03 MHz between source register \"testfreq:inst3\|count2\[1\]\" and destination register \"testfreq:inst3\|count2\[19\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.610 ns + Longest register register " "Info: + Longest register to register delay is 2.610 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns testfreq:inst3\|count2\[1\] 1 REG LC_X23_Y10_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y10_N1; Fanout = 4; REG Node = 'testfreq:inst3\|count2\[1\]'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { testfreq:inst3|count2[1] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.564 ns) 1.093 ns testfreq:inst3\|count2\[1\]~594 2 COMB LC_X23_Y10_N1 2 " "Info: 2: + IC(0.529 ns) + CELL(0.564 ns) = 1.093 ns; Loc. = LC_X23_Y10_N1; Fanout = 2; COMB Node = 'testfreq:inst3\|count2\[1\]~594'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.093 ns" { testfreq:inst3|count2[1] testfreq:inst3|count2[1]~594 } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.171 ns testfreq:inst3\|count2\[2\]~593 3 COMB LC_X23_Y10_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.171 ns; Loc. = LC_X23_Y10_N2; Fanout = 2; COMB Node = 'testfreq:inst3\|count2\[2\]~593'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { testfreq:inst3|count2[1]~594 testfreq:inst3|count2[2]~593 } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.249 ns testfreq:inst3\|count2\[3\]~592 4 COMB LC_X23_Y10_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.249 ns; Loc. = LC_X23_Y10_N3; Fanout = 2; COMB Node = 'testfreq:inst3\|count2\[3\]~592'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { testfreq:inst3|count2[2]~593 testfreq:inst3|count2[3]~592 } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.427 ns testfreq:inst3\|count2\[4\]~591 5 COMB LC_X23_Y10_N4 6 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.427 ns; Loc. = LC_X23_Y10_N4; Fanout = 6; COMB Node = 'testfreq:inst3\|count2\[4\]~591'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { testfreq:inst3|count2[3]~592 testfreq:inst3|count2[4]~591 } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 1.635 ns testfreq:inst3\|count2\[9\]~586 6 COMB LC_X23_Y10_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.208 ns) = 1.635 ns; Loc. = LC_X23_Y10_N9; Fanout = 6; COMB Node = 'testfreq:inst3\|count2\[9\]~586'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { testfreq:inst3|count2[4]~591 testfreq:inst3|count2[9]~586 } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.771 ns testfreq:inst3\|count2\[14\]~581 7 COMB LC_X23_Y9_N4 5 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 1.771 ns; Loc. = LC_X23_Y9_N4; Fanout = 5; COMB Node = 'testfreq:inst3\|count2\[14\]~581'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { testfreq:inst3|count2[9]~586 testfreq:inst3|count2[14]~581 } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.610 ns testfreq:inst3\|count2\[19\] 8 REG LC_X23_Y9_N9 2 " "Info: 8: + IC(0.000 ns) + CELL(0.839 ns) = 2.610 ns; Loc. = LC_X23_Y9_N9; Fanout = 2; REG Node = 'testfreq:inst3\|count2\[19\]'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.839 ns" { testfreq:inst3|count2[14]~581 testfreq:inst3|count2[19] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 79.73 % ) " "Info: Total cell delay = 2.081 ns ( 79.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.529 ns ( 20.27 % ) " "Info: Total interconnect delay = 0.529 ns ( 20.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.610 ns" { testfreq:inst3|count2[1] testfreq:inst3|count2[1]~594 testfreq:inst3|count2[2]~593 testfreq:inst3|count2[3]~592 testfreq:inst3|count2[4]~591 testfreq:inst3|count2[9]~586 testfreq:inst3|count2[14]~581 testfreq:inst3|count2[19] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.610 ns" { testfreq:inst3|count2[1] testfreq:inst3|count2[1]~594 testfreq:inst3|count2[2]~593 testfreq:inst3|count2[3]~592 testfreq:inst3|count2[4]~591 testfreq:inst3|count2[9]~586 testfreq:inst3|count2[14]~581 testfreq:inst3|count2[19] } { 0.000ns 0.529ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 7.280 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 7.280 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clock 1 CLK PIN_143 20 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_143; Fanout = 20; CLK Node = 'clock'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/testfreq/Block1.bdf" { { 264 -88 80 280 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.094 ns) + CELL(0.711 ns) 7.280 ns testfreq:inst3\|count2\[19\] 2 REG LC_X23_Y9_N9 2 " "Info: 2: + IC(5.094 ns) + CELL(0.711 ns) = 7.280 ns; Loc. = LC_X23_Y9_N9; Fanout = 2; REG Node = 'testfreq:inst3\|count2\[19\]'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.805 ns" { clock testfreq:inst3|count2[19] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 30.03 % ) " "Info: Total cell delay = 2.186 ns ( 30.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.094 ns ( 69.97 % ) " "Info: Total interconnect delay = 5.094 ns ( 69.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.280 ns" { clock testfreq:inst3|count2[19] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "7.280 ns" { clock clock~out0 testfreq:inst3|count2[19] } { 0.000ns 0.000ns 5.094ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 7.280 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 7.280 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clock 1 CLK PIN_143 20 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_143; Fanout = 20; CLK Node = 'clock'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/testfreq/Block1.bdf" { { 264 -88 80 280 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.094 ns) + CELL(0.711 ns) 7.280 ns testfreq:inst3\|count2\[1\] 2 REG LC_X23_Y10_N1 4 " "Info: 2: + IC(5.094 ns) + CELL(0.711 ns) = 7.280 ns; Loc. = LC_X23_Y10_N1; Fanout = 4; REG Node = 'testfreq:inst3\|count2\[1\]'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.805 ns" { clock testfreq:inst3|count2[1] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 30.03 % ) " "Info: Total cell delay = 2.186 ns ( 30.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.094 ns ( 69.97 % ) " "Info: Total interconnect delay = 5.094 ns ( 69.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.280 ns" { clock testfreq:inst3|count2[1] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "7.280 ns" { clock clock~out0 testfreq:inst3|count2[1] } { 0.000ns 0.000ns 5.094ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.280 ns" { clock testfreq:inst3|count2[19] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "7.280 ns" { clock clock~out0 testfreq:inst3|count2[19] } { 0.000ns 0.000ns 5.094ns } { 0.000ns 1.475ns 0.711ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.280 ns" { clock testfreq:inst3|count2[1] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "7.280 ns" { clock clock~out0 testfreq:inst3|count2[1] } { 0.000ns 0.000ns 5.094ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 38 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 38 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.610 ns" { testfreq:inst3|count2[1] testfreq:inst3|count2[1]~594 testfreq:inst3|count2[2]~593 testfreq:inst3|count2[3]~592 testfreq:inst3|count2[4]~591 testfreq:inst3|count2[9]~586 testfreq:inst3|count2[14]~581 testfreq:inst3|count2[19] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.610 ns" { testfreq:inst3|count2[1] testfreq:inst3|count2[1]~594 testfreq:inst3|count2[2]~593 testfreq:inst3|count2[3]~592 testfreq:inst3|count2[4]~591 testfreq:inst3|count2[9]~586 testfreq:inst3|count2[14]~581 testfreq:inst3|count2[19] } { 0.000ns 0.529ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.280 ns" { clock testfreq:inst3|count2[19] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "7.280 ns" { clock clock~out0 testfreq:inst3|count2[19] } { 0.000ns 0.000ns 5.094ns } { 0.000ns 1.475ns 0.711ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.280 ns" { clock testfreq:inst3|count2[1] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "7.280 ns" { clock clock~out0 testfreq:inst3|count2[1] } { 0.000ns 0.000ns 5.094ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { testfreq:inst3|count2[19] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { testfreq:inst3|count2[19] } { } { } "" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/testfreq/testfreq.vhd" 38 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
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