testfreq.tan.qmsg

利用示波器的X和Y通道输出采样波形图形 注：显示两个周期。扫频频率100Hz

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "testfreq:inst3\|count2\[9\] testfreq:inst3\|freq1\[9\] clk 4.648 ns " "Info: Found hold time violation between source  pin or register \"testfreq:inst3\|count2\[9\]\" and destination pin or register \"testfreq:inst3\|freq1\[9\]\" for clock \"clk\" (Hold time is 4.648 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.728 ns + Largest " "Info: + Largest clock skew is 5.728 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.471 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.471 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 197 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 197; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/复件 testfreq/Block1.bdf" { { 160 -104 64 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns testfreq:inst3\|clr 2 REG LC_X9_Y2_N1 23 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X9_Y2_N1; Fanout = 23; REG Node = 'testfreq:inst3\|clr'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk testfreq:inst3|clr } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.302 ns) + CELL(0.114 ns) 4.370 ns testfreq:inst3\|comb~0 3 COMB LC_X8_Y6_N1 20 " "Info: 3: + IC(1.302 ns) + CELL(0.114 ns) = 4.370 ns; Loc. = LC_X8_Y6_N1; Fanout = 20; COMB Node = 'testfreq:inst3\|comb~0'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.416 ns" { testfreq:inst3|clr testfreq:inst3|comb~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.987 ns) + CELL(0.114 ns) 8.471 ns testfreq:inst3\|freq1\[9\] 4 REG LC_X20_Y4_N0 1 " "Info: 4: + IC(3.987 ns) + CELL(0.114 ns) = 8.471 ns; Loc. = LC_X20_Y4_N0; Fanout = 1; REG Node = 'testfreq:inst3\|freq1\[9\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.101 ns" { testfreq:inst3|comb~0 testfreq:inst3|freq1[9] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.632 ns ( 31.07 % ) " "Info: Total cell delay = 2.632 ns ( 31.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.839 ns ( 68.93 % ) " "Info: Total interconnect delay = 5.839 ns ( 68.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.471 ns" { clk testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[9] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "8.471 ns" { clk clk~out0 testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[9] } { 0.000ns 0.000ns 0.550ns 1.302ns 3.987ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.743 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 197 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 197; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/复件 testfreq/Block1.bdf" { { 160 -104 64 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns testfreq:inst3\|count2\[9\] 2 REG LC_X20_Y4_N9 3 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X20_Y4_N9; Fanout = 3; REG Node = 'testfreq:inst3\|count2\[9\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.274 ns" { clk testfreq:inst3|count2[9] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.48 % ) " "Info: Total cell delay = 2.180 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { clk testfreq:inst3|count2[9] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 testfreq:inst3|count2[9] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.471 ns" { clk testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[9] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "8.471 ns" { clk clk~out0 testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[9] } { 0.000ns 0.000ns 0.550ns 1.302ns 3.987ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.114ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { clk testfreq:inst3|count2[9] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 testfreq:inst3|count2[9] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 39 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.856 ns - Shortest register register " "Info: - Shortest register to register delay is 0.856 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns testfreq:inst3\|count2\[9\] 1 REG LC_X20_Y4_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y4_N9; Fanout = 3; REG Node = 'testfreq:inst3\|count2\[9\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { testfreq:inst3|count2[9] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.564 ns) + CELL(0.292 ns) 0.856 ns testfreq:inst3\|freq1\[9\] 2 REG LC_X20_Y4_N0 1 " "Info: 2: + IC(0.564 ns) + CELL(0.292 ns) = 0.856 ns; Loc. = LC_X20_Y4_N0; Fanout = 1; REG Node = 'testfreq:inst3\|freq1\[9\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.856 ns" { testfreq:inst3|count2[9] testfreq:inst3|freq1[9] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.292 ns ( 34.11 % ) " "Info: Total cell delay = 0.292 ns ( 34.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.564 ns ( 65.89 % ) " "Info: Total interconnect delay = 0.564 ns ( 65.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.856 ns" { testfreq:inst3|count2[9] testfreq:inst3|freq1[9] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "0.856 ns" { testfreq:inst3|count2[9] testfreq:inst3|freq1[9] } { 0.000ns 0.564ns } { 0.000ns 0.292ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 39 -1 0 } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.471 ns" { clk testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[9] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "8.471 ns" { clk clk~out0 testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[9] } { 0.000ns 0.000ns 0.550ns 1.302ns 3.987ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.114ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { clk testfreq:inst3|count2[9] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 testfreq:inst3|count2[9] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.856 ns" { testfreq:inst3|count2[9] testfreq:inst3|freq1[9] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "0.856 ns" { testfreq:inst3|count2[9] testfreq:inst3|freq1[9] } { 0.000ns 0.564ns } { 0.000ns 0.292ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "testfreq:inst3\|count2\[19\] clock clk 9.006 ns register " "Info: tsu for register \"testfreq:inst3\|count2\[19\]\" (data pin = \"clock\", clock pin = \"clk\") is 9.006 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.712 ns + Longest pin register " "Info: + Longest pin to register delay is 11.712 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clock 1 PIN PIN_144 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_144; Fanout = 2; PIN Node = 'clock'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/复件 testfreq/Block1.bdf" { { 264 -88 80 280 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.308 ns) + CELL(0.442 ns) 9.225 ns testfreq:inst3\|count2\[19\]~957 2 COMB LC_X16_Y4_N6 20 " "Info: 2: + IC(7.308 ns) + CELL(0.442 ns) = 9.225 ns; Loc. = LC_X16_Y4_N6; Fanout = 20; COMB Node = 'testfreq:inst3\|count2\[19\]~957'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.750 ns" { clock testfreq:inst3|count2[19]~957 } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.620 ns) + CELL(0.867 ns) 11.712 ns testfreq:inst3\|count2\[19\] 3 REG LC_X20_Y3_N9 2 " "Info: 3: + IC(1.620 ns) + CELL(0.867 ns) = 11.712 ns; Loc. = LC_X20_Y3_N9; Fanout = 2; REG Node = 'testfreq:inst3\|count2\[19\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.487 ns" { testfreq:inst3|count2[19]~957 testfreq:inst3|count2[19] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.784 ns ( 23.77 % ) " "Info: Total cell delay = 2.784 ns ( 23.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.928 ns ( 76.23 % ) " "Info: Total interconnect delay = 8.928 ns ( 76.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.712 ns" { clock testfreq:inst3|count2[19]~957 testfreq:inst3|count2[19] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "11.712 ns" { clock clock~out0 testfreq:inst3|count2[19]~957 testfreq:inst3|count2[19] } { 0.000ns 0.000ns 7.308ns 1.620ns } { 0.000ns 1.475ns 0.442ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 39 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.743 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 197 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 197; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/复件 testfreq/Block1.bdf" { { 160 -104 64 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns testfreq:inst3\|count2\[19\] 2 REG LC_X20_Y3_N9 2 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X20_Y3_N9; Fanout = 2; REG Node = 'testfreq:inst3\|count2\[19\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.274 ns" { clk testfreq:inst3|count2[19] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.48 % ) " "Info: Total cell delay = 2.180 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { clk testfreq:inst3|count2[19] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 testfreq:inst3|count2[19] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.712 ns" { clock testfreq:inst3|count2[19]~957 testfreq:inst3|count2[19] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "11.712 ns" { clock clock~out0 testfreq:inst3|count2[19]~957 testfreq:inst3|count2[19] } { 0.000ns 0.000ns 7.308ns 1.620ns } { 0.000ns 1.475ns 0.442ns 0.867ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { clk testfreq:inst3|count2[19] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 testfreq:inst3|count2[19] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk wie\[3\] LED:inst1\|wei\[3\] 13.403 ns register " "Info: tco from clock \"clk\" to destination pin \"wie\[3\]\" through register \"LED:inst1\|wei\[3\]\" is 13.403 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.555 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.555 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 197 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 197; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/复件 testfreq/Block1.bdf" { { 160 -104 64 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns LED:inst1\|clk1 2 REG LC_X10_Y6_N5 17 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X10_Y6_N5; Fanout = 17; REG Node = 'LED:inst1\|clk1'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk LED:inst1|clk1 } "NODE_NAME" } } { "LED.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/LED.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.880 ns) + CELL(0.711 ns) 7.555 ns LED:inst1\|wei\[3\] 3 REG LC_X15_Y8_N5 1 " "Info: 3: + IC(3.880 ns) + CELL(0.711 ns) = 7.555 ns; Loc. = LC_X15_Y8_N5; Fanout = 1; REG Node = 'LED:inst1\|wei\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.591 ns" { LED:inst1|clk1 LED:inst1|wei[3] } "NODE_NAME" } } { "LED.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/LED.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 41.23 % ) " "Info: Total cell delay = 3.115 ns ( 41.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.440 ns ( 58.77 % ) " "Info: Total interconnect delay = 4.440 ns ( 58.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.555 ns" { clk LED:inst1|clk1 LED:inst1|wei[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "7.555 ns" { clk clk~out0 LED:inst1|clk1 LED:inst1|wei[3] } { 0.000ns 0.000ns 0.560ns 3.880ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "LED.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/LED.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.624 ns + Longest register pin " "Info: + Longest register to pin delay is 5.624 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LED:inst1\|wei\[3\] 1 REG LC_X15_Y8_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y8_N5; Fanout = 1; REG Node = 'LED:inst1\|wei\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { LED:inst1|wei[3] } "NODE_NAME" } } { "LED.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/LED.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(2.124 ns) 5.624 ns wie\[3\] 2 PIN PIN_36 0 " "Info: 2: + IC(3.500 ns) + CELL(2.124 ns) = 5.624 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'wie\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.624 ns" { LED:inst1|wei[3] wie[3] } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/复件 testfreq/Block1.bdf" { { 216 640 816 232 "wie\[5..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 37.77 % ) " "Info: Total cell delay = 2.124 ns ( 37.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns ( 62.23 % ) " "Info: Total interconnect delay = 3.500 ns ( 62.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.624 ns" { LED:inst1|wei[3] wie[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.624 ns" { LED:inst1|wei[3] wie[3] } { 0.000ns 3.500ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.555 ns" { clk LED:inst1|clk1 LED:inst1|wei[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "7.555 ns" { clk clk~out0 LED:inst1|clk1 LED:inst1|wei[3] } { 0.000ns 0.000ns 0.560ns 3.880ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.624 ns" { LED:inst1|wei[3] wie[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.624 ns" { LED:inst1|wei[3] wie[3] } { 0.000ns 3.500ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "testfreq:inst3\|count2\[0\] clock clk -7.193 ns register " "Info: th for register \"testfreq:inst3\|count2\[0\]\" (data pin = \"clock\", clock pin = \"clk\") is -7.193 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.743 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 197 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 197; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/复件 testfreq/Block1.bdf" { { 160 -104 64 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns testfreq:inst3\|count2\[0\] 2 REG LC_X16_Y4_N3 5 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X16_Y4_N3; Fanout = 5; REG Node = 'testfreq:inst3\|count2\[0\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.274 ns" { clk testfreq:inst3|count2[0] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.48 % ) " "Info: Total cell delay = 2.180 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { clk testfreq:inst3|count2[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 testfreq:inst3|count2[0] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 39 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.951 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.951 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clock 1 PIN PIN_144 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_144; Fanout = 2; PIN Node = 'clock'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/复件 testfreq/Block1.bdf" { { 264 -88 80 280 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.308 ns) + CELL(0.442 ns) 9.225 ns testfreq:inst3\|count2\[19\]~957 2 COMB LC_X16_Y4_N6 20 " "Info: 2: + IC(7.308 ns) + CELL(0.442 ns) = 9.225 ns; Loc. = LC_X16_Y4_N6; Fanout = 20; COMB Node = 'testfreq:inst3\|count2\[19\]~957'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.750 ns" { clock testfreq:inst3|count2[19]~957 } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.417 ns) + CELL(0.309 ns) 9.951 ns testfreq:inst3\|count2\[0\] 3 REG LC_X16_Y4_N3 5 " "Info: 3: + IC(0.417 ns) + CELL(0.309 ns) = 9.951 ns; Loc. = LC_X16_Y4_N3; Fanout = 5; REG Node = 'testfreq:inst3\|count2\[0\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.726 ns" { testfreq:inst3|count2[19]~957 testfreq:inst3|count2[0] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.226 ns ( 22.37 % ) " "Info: Total cell delay = 2.226 ns ( 22.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.725 ns ( 77.63 % ) " "Info: Total interconnect delay = 7.725 ns ( 77.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.951 ns" { clock testfreq:inst3|count2[19]~957 testfreq:inst3|count2[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "9.951 ns" { clock clock~out0 testfreq:inst3|count2[19]~957 testfreq:inst3|count2[0] } { 0.000ns 0.000ns 7.308ns 0.417ns } { 0.000ns 1.475ns 0.442ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { clk testfreq:inst3|count2[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 testfreq:inst3|count2[0] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.951 ns" { clock testfreq:inst3|count2[19]~957 testfreq:inst3|count2[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "9.951 ns" { clock clock~out0 testfreq:inst3|count2[19]~957 testfreq:inst3|count2[0] } { 0.000ns 0.000ns 7.308ns 0.417ns } { 0.000ns 1.475ns 0.442ns 0.309ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}