testfreq.tan.qmsg

利用示波器的X和Y通道输出采样波形图形 注：显示两个周期。扫频频率100Hz

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/复件 testfreq/Block1.bdf" { { 160 -104 64 176 "clk" "" } } } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "testfreq:inst3\|comb~0 " "Info: Detected gated clock \"testfreq:inst3\|comb~0\" as buffer" {  } { { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "testfreq:inst3\|comb~0" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "testfreq:inst3\|clk1 " "Info: Detected ripple clock \"testfreq:inst3\|clk1\" as buffer" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 11 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "testfreq:inst3\|clk1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "testfreq:inst3\|clr " "Info: Detected ripple clock \"testfreq:inst3\|clr\" as buffer" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 11 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "testfreq:inst3\|clr" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "LED:inst1\|clk1 " "Info: Detected ripple clock \"LED:inst1\|clk1\" as buffer" {  } { { "LED.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/LED.vhd" 14 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "LED:inst1\|clk1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register testfreq:inst3\|freq1\[0\] register testfreq:inst3\|freq\[0\] 84.43 MHz 11.844 ns Internal " "Info: Clock \"clk\" has Internal fmax of 84.43 MHz between source register \"testfreq:inst3\|freq1\[0\]\" and destination register \"testfreq:inst3\|freq\[0\]\" (period= 11.844 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.148 ns + Longest register register " "Info: + Longest register to register delay is 0.148 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns testfreq:inst3\|freq1\[0\] 1 REG LC_X16_Y4_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y4_N9; Fanout = 1; REG Node = 'testfreq:inst3\|freq1\[0\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { testfreq:inst3|freq1[0] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.148 ns) 0.148 ns testfreq:inst3\|freq\[0\] 2 REG LC_X16_Y4_N9 2 " "Info: 2: + IC(0.000 ns) + CELL(0.148 ns) = 0.148 ns; Loc. = LC_X16_Y4_N9; Fanout = 2; REG Node = 'testfreq:inst3\|freq\[0\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.148 ns" { testfreq:inst3|freq1[0] testfreq:inst3|freq[0] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.148 ns ( 100.00 % ) " "Info: Total cell delay = 0.148 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.148 ns" { testfreq:inst3|freq1[0] testfreq:inst3|freq[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "0.148 ns" { testfreq:inst3|freq1[0] testfreq:inst3|freq[0] } { 0.000ns 0.000ns } { 0.000ns 0.148ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.737 ns - Smallest " "Info: - Smallest clock skew is -5.737 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.743 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 197 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 197; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/复件 testfreq/Block1.bdf" { { 160 -104 64 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns testfreq:inst3\|freq\[0\] 2 REG LC_X16_Y4_N9 2 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X16_Y4_N9; Fanout = 2; REG Node = 'testfreq:inst3\|freq\[0\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.274 ns" { clk testfreq:inst3|freq[0] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.48 % ) " "Info: Total cell delay = 2.180 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { clk testfreq:inst3|freq[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 testfreq:inst3|freq[0] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.480 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.480 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 197 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 197; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/复件 testfreq/Block1.bdf" { { 160 -104 64 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns testfreq:inst3\|clr 2 REG LC_X9_Y2_N1 23 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X9_Y2_N1; Fanout = 23; REG Node = 'testfreq:inst3\|clr'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk testfreq:inst3|clr } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.302 ns) + CELL(0.114 ns) 4.370 ns testfreq:inst3\|comb~0 3 COMB LC_X8_Y6_N1 20 " "Info: 3: + IC(1.302 ns) + CELL(0.114 ns) = 4.370 ns; Loc. = LC_X8_Y6_N1; Fanout = 20; COMB Node = 'testfreq:inst3\|comb~0'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.416 ns" { testfreq:inst3|clr testfreq:inst3|comb~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.996 ns) + CELL(0.114 ns) 8.480 ns testfreq:inst3\|freq1\[0\] 4 REG LC_X16_Y4_N9 1 " "Info: 4: + IC(3.996 ns) + CELL(0.114 ns) = 8.480 ns; Loc. = LC_X16_Y4_N9; Fanout = 1; REG Node = 'testfreq:inst3\|freq1\[0\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.110 ns" { testfreq:inst3|comb~0 testfreq:inst3|freq1[0] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.632 ns ( 31.04 % ) " "Info: Total cell delay = 2.632 ns ( 31.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.848 ns ( 68.96 % ) " "Info: Total interconnect delay = 5.848 ns ( 68.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.480 ns" { clk testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "8.480 ns" { clk clk~out0 testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[0] } { 0.000ns 0.000ns 0.550ns 1.302ns 3.996ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { clk testfreq:inst3|freq[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 testfreq:inst3|freq[0] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.480 ns" { clk testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "8.480 ns" { clk clk~out0 testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[0] } { 0.000ns 0.000ns 0.550ns 1.302ns 3.996ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.114ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 -1 0 } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 55 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.148 ns" { testfreq:inst3|freq1[0] testfreq:inst3|freq[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "0.148 ns" { testfreq:inst3|freq1[0] testfreq:inst3|freq[0] } { 0.000ns 0.000ns } { 0.000ns 0.148ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { clk testfreq:inst3|freq[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 testfreq:inst3|freq[0] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.480 ns" { clk testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "8.480 ns" { clk clk~out0 testfreq:inst3|clr testfreq:inst3|comb~0 testfreq:inst3|freq1[0] } { 0.000ns 0.000ns 0.550ns 1.302ns 3.996ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.114ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 154 " "Warning: Circuit may not operate. Detected 154 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}