testfreq.map.qmsg

利用示波器的X和Y通道输出采样波形图形 注：显示两个周期。扫频频率100Hz

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 23 10:01:03 2007 " "Info: Processing started: Thu Aug 23 10:01:03 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off testfreq -c testfreq " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off testfreq -c testfreq" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Dec_to_BCD.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Dec_to_BCD.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Dec_to_BCD-zx " "Info: Found design unit 1: Dec_to_BCD-zx" {  } { { "Dec_to_BCD.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/Dec_to_BCD.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Dec_to_BCD " "Info: Found entity 1: Dec_to_BCD" {  } { { "Dec_to_BCD.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/Dec_to_BCD.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LED.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file LED.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LED-zx " "Info: Found design unit 1: LED-zx" {  } { { "LED.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/LED.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 LED " "Info: Found entity 1: LED" {  } { { "LED.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/LED.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "testfreq.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file testfreq.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 testfreq-zx " "Info: Found design unit 1: testfreq-zx" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 testfreq " "Info: Found entity 1: testfreq" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/复件 testfreq/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Block1 " "Info: Elaborating entity \"Block1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LED LED:inst1 " "Info: Elaborating entity \"LED\" for hierarchy \"LED:inst1\"" {  } { { "Block1.bdf" "inst1" { Schematic "D:/Project/Quartus II/复件 testfreq/Block1.bdf" { { 192 504 640 352 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Dec_to_BCD Dec_to_BCD:inst " "Info: Elaborating entity \"Dec_to_BCD\" for hierarchy \"Dec_to_BCD:inst\"" {  } { { "Block1.bdf" "inst" { Schematic "D:/Project/Quartus II/复件 testfreq/Block1.bdf" { { 208 240 384 368 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "testfreq testfreq:inst3 " "Info: Elaborating entity \"testfreq\" for hierarchy \"testfreq:inst3\"" {  } { { "Block1.bdf" "inst3" { Schematic "D:/Project/Quartus II/复件 testfreq/Block1.bdf" { { 224 80 208 320 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "freq1 testfreq.vhd(36) " "Warning (10631): VHDL Process Statement warning at testfreq.vhd(36): inferring latch(es) for signal or variable \"freq1\", which holds its previous value in one or more paths through the process" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk testfreq.vhd(55) " "Warning (10492): VHDL Process Statement warning at testfreq.vhd(55): signal \"clk\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 55 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[0\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[0\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[1\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[1\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[2\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[2\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[3\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[3\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[4\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[4\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[5\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[5\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[6\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[6\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[7\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[7\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[8\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[8\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[9\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[9\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[10\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[10\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[11\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[11\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[12\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[12\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[13\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[13\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[14\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[14\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[15\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[15\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[16\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[16\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[17\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[17\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[18\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[18\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "freq1\[19\] testfreq.vhd(36) " "Info (10041): Verilog HDL or VHDL info at testfreq.vhd(36): inferred latch for \"freq1\[19\]\"" {  } { { "testfreq.vhd" "" { Text "D:/Project/Quartus II/复件 testfreq/testfreq.vhd" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "466 " "Info: Implemented 466 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "451 " "Info: Implemented 451 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Allocated 140 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 23 10:01:09 2007 " "Info: Processing ended: Thu Aug 23 10:01:09 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}