testfreq.vhd

来自「利用示波器的X和Y通道输出采样波形图形 注：显示两个周期。扫频频率100Hz」· VHDL 代码 · 共 59 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
entity testfreq is
	port( clk :in std_logic;
		  clock: in std_logic;
		  freq: out integer range 0 to 999999);
end testfreq;

ARCHITECTURE zx OF testfreq IS
	signal clk1,clr: std_logic;
	signal freq1:integer range 0 to 999999;
begin

	
	process(clk)
		variable count :  integer range 0 to  50000002;
	begin
		if(clk'event and clk='1') then
			if(count=50000002) then count:=0; clr<='1';
			else count:=count+1; clr<='0';
			end if;
		end if;
	end process;

	process(clk)
		variable count1 :  integer range 0 to  49999999;
	begin
		if(clk'event and clk='1') then
			if(count1=49999999) then count1:=0; clk1<='1';
			else count1:=count1+1; clk1<='0';
			end if;
		end if;
	end process;
	
	process(clk,clock,clk1,clr)
		variable count2,count3: integer range 0 to 999999;
	begin
		if(clr='1') then count2:=0;
		elsif(clk1='1') then freq1<=count2;
--		elsif(clock'event and clock='1') then 
--			count2:=count2+1;
--		end if;
		elsif(clock='0') then count3:=0;
		elsif(clk'event and clk='1') then 
			count3:=count3+1;
			if(count3=50) then count2:=count2+1;
			else count2:=count2;
			end if;
		end if;
	end process;
	
	process(clk1)
	begin
		if(clk'event and clk='1') then freq<=freq1;
		end if;
	end process;
	
end zx;