dec_to_bcd.vhd

来自「利用示波器的X和Y通道输出采样波形图形 注：显示两个周期。扫频频率100Hz」· VHDL 代码 · 共 73 行

--**********************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
--*********************************************************
ENTITY Dec_to_BCD IS                                                                     --?????
     port( clk: in std_logic; 
		   num: in integer range 0 to 999999;
		   n1,n2,n3,n4,n5,n6:out std_logic_vector(3 downto 0));
END Dec_to_BCD;
--*********************************************************
ARCHITECTURE zx OF Dec_to_BCD IS
begin 
	process(clk,num )
		variable com:integer range 0 to 999999;
		variable n11,n22,n33,n44,n55,n66:std_logic_vector(3 downto 0);

	begin 
	    if( clk 'event and clk='1') then
           if(com<num) then
               if(n11=9 and n22=9 and n33=9 and n44=9 and n55=9) then                             
                  n11:="0000";                                     
                  n22:="0000";                                        
                  n33:="0000";
			      n44:="0000";                                      
                  n55:="0000";
				  n66:=n66+1;                                     
                  com:=com+1;                                     
               elsif(n11=9 and n22=9 and n33=9 and n44=9) then                             
                  n11:="0000";                                     
                  n22:="0000";                                        
                  n33:="0000";
			      n44:="0000";                                      
                  n55:=n55+1;                                     
                  com:=com+1;                                     
              elsif(n11=9 and n22=9 and n33=9) then                             
                  n11:="0000";                                     
                  n22:="0000";                                        
                  n33:="0000";                                      
                  n44:=n44+1;                                     
                  com:=com+1;                                     
               elsif(n11=9 and n22=9) then
                  n11:="0000";
                  n22:="0000";     
                  n33:=n33+1;
                  com:=com+1; 
               elsif(n11=9) then
                  n11:="0000";
                  n22:=n22+1;
                  com:=com+1;
               else
                  n11:=n11+1;
                  com:=com+1;
               end if;
          else
                  n1<=n11;
				  n2<=n22; 
                  n3<=n33;
                  n4<=n44;
				  n5<=n55;
				  n6<=n66;
                  com:=0;
                  n11:="0000";
                  n22:="0000";
                  n33:="0000";
                  n44:="0000";
				  n55:="0000";
				  n66:="0000";
           end if;
        end if;
    end process;
END zx;