testfreq.fit.smsg

利用示波器的X和Y通道输出采样波形图形 注：显示两个周期。扫频频率100Hz

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Aug 30 02:46:48 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off testfreq -c testfreq
Info: Selected device EP1C3T144C8 for design "testfreq"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 417 of 417 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C6T144C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 12
    Info: Pin ~ASDO~ is reserved at location 25
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clk" to use Global clock in PIN 16
Info: Automatically promoted signal "clock" to use Global clock
Info: Pin "clock" drives global clock, but is not placed in a dedicated clock pin position
Info: Automatically promoted signal "testfreq:inst3|comb~0" to use Global clock
Info: Automatically promoted some destinations of signal "LED:inst1|clk1" to use Global clock
    Info: Destination "LED:inst1|clk1" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "testfreq:inst3|clr" to use Global clock
    Info: Destination "testfreq:inst3|comb~0" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 8.116 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X25_Y10; Fanout = 2; REG Node = 'testfreq:inst3|freq[0]'
    Info: 2: + IC(1.668 ns) + CELL(0.432 ns) = 2.100 ns; Loc. = LAB_X22_Y7; Fanout = 1; COMB Node = 'Dec_to_BCD:inst|LessThan0~364COUT1'
    Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 2.180 ns; Loc. = LAB_X22_Y7; Fanout = 1; COMB Node = 'Dec_to_BCD:inst|LessThan0~359COUT1'
    Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 2.260 ns; Loc. = LAB_X22_Y7; Fanout = 1; COMB Node = 'Dec_to_BCD:inst|LessThan0~354COUT1'
    Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 2.340 ns; Loc. = LAB_X22_Y7; Fanout = 1; COMB Node = 'Dec_to_BCD:inst|LessThan0~349COUT1'
    Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 2.598 ns; Loc. = LAB_X22_Y7; Fanout = 1; COMB Node = 'Dec_to_BCD:inst|LessThan0~344'
    Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 2.734 ns; Loc. = LAB_X22_Y7; Fanout = 1; COMB Node = 'Dec_to_BCD:inst|LessThan0~319'
    Info: 8: + IC(0.000 ns) + CELL(0.136 ns) = 2.870 ns; Loc. = LAB_X22_Y6; Fanout = 1; COMB Node = 'Dec_to_BCD:inst|LessThan0~294'
    Info: 9: + IC(0.000 ns) + CELL(0.679 ns) = 3.549 ns; Loc. = LAB_X22_Y6; Fanout = 56; COMB Node = 'Dec_to_BCD:inst|LessThan0~267'
    Info: 10: + IC(1.369 ns) + CELL(0.590 ns) = 5.508 ns; Loc. = LAB_X12_Y6; Fanout = 4; COMB Node = 'Dec_to_BCD:inst|n44[0]~134'
    Info: 11: + IC(1.496 ns) + CELL(1.112 ns) = 8.116 ns; Loc. = LAB_X15_Y7; Fanout = 5; REG Node = 'Dec_to_BCD:inst|n44[0]'
    Info: Total cell delay = 3.583 ns ( 44.15 % )
    Info: Total interconnect delay = 4.533 ns ( 55.85 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 2% of the available device resources. Peak interconnect usage is 3%
    Info: The peak interconnect region extends from location X0_Y0 to location X13_Y14
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Allocated 162 megabytes of memory during processing
    Info: Processing ended: Thu Aug 30 02:46:53 2007
    Info: Elapsed time: 00:00:05