altsyncram_njc1.tdf

这是一个FPGA的BCD码编码器设计.编译后可以下载到ALTEA的器件中仿真.

			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "RAMs.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 4,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 15,
			PORT_A_LOGICAL_RAM_DEPTH = 16,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 4,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 4,
			PORT_B_LAST_ADDRESS = 15,
			PORT_B_LOGICAL_RAM_DEPTH = 16,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a5 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "RAMs.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 4,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 15,
			PORT_A_LOGICAL_RAM_DEPTH = 16,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 4,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 5,
			PORT_B_LAST_ADDRESS = 15,
			PORT_B_LOGICAL_RAM_DEPTH = 16,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a6 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "RAMs.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 4,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 15,
			PORT_A_LOGICAL_RAM_DEPTH = 16,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 4,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 6,
			PORT_B_LAST_ADDRESS = 15,
			PORT_B_LOGICAL_RAM_DEPTH = 16,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a7 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "RAMs.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 4,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 15,
			PORT_A_LOGICAL_RAM_DEPTH = 16,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 4,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 7,
			PORT_B_LAST_ADDRESS = 15,
			PORT_B_LOGICAL_RAM_DEPTH = 16,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	address_a_wire[3..0]	: WIRE;
	address_b_wire[3..0]	: WIRE;

BEGIN 
	ram_block1a[7..0].clk0 = clock0;
	ram_block1a[7..0].clk1 = clock1;
	ram_block1a[0].portaaddr[] = ( B"000000000000", address_a_wire[3..0]);
	ram_block1a[1].portaaddr[] = ( B"000000000000", address_a_wire[3..0]);
	ram_block1a[2].portaaddr[] = ( B"000000000000", address_a_wire[3..0]);
	ram_block1a[3].portaaddr[] = ( B"000000000000", address_a_wire[3..0]);
	ram_block1a[4].portaaddr[] = ( B"000000000000", address_a_wire[3..0]);
	ram_block1a[5].portaaddr[] = ( B"000000000000", address_a_wire[3..0]);
	ram_block1a[6].portaaddr[] = ( B"000000000000", address_a_wire[3..0]);
	ram_block1a[7].portaaddr[] = ( B"000000000000", address_a_wire[3..0]);
	ram_block1a[0].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[0..0]);
	ram_block1a[1].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[1..1]);
	ram_block1a[2].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[2..2]);
	ram_block1a[3].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[3..3]);
	ram_block1a[4].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[4..4]);
	ram_block1a[5].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[5..5]);
	ram_block1a[6].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[6..6]);
	ram_block1a[7].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[7..7]);
	ram_block1a[7..0].portawe = wren_a;
	ram_block1a[0].portbaddr[] = ( B"000000000000", address_b_wire[3..0]);
	ram_block1a[1].portbaddr[] = ( B"000000000000", address_b_wire[3..0]);
	ram_block1a[2].portbaddr[] = ( B"000000000000", address_b_wire[3..0]);
	ram_block1a[3].portbaddr[] = ( B"000000000000", address_b_wire[3..0]);
	ram_block1a[4].portbaddr[] = ( B"000000000000", address_b_wire[3..0]);
	ram_block1a[5].portbaddr[] = ( B"000000000000", address_b_wire[3..0]);
	ram_block1a[6].portbaddr[] = ( B"000000000000", address_b_wire[3..0]);
	ram_block1a[7].portbaddr[] = ( B"000000000000", address_b_wire[3..0]);
	ram_block1a[0].portbrewe = B"1";
	ram_block1a[1].portbrewe = B"1";
	ram_block1a[2].portbrewe = B"1";
	ram_block1a[3].portbrewe = B"1";
	ram_block1a[4].portbrewe = B"1";
	ram_block1a[5].portbrewe = B"1";
	ram_block1a[6].portbrewe = B"1";
	ram_block1a[7].portbrewe = B"1";
	address_a_wire[] = address_a[];
	address_b_wire[] = address_b[];
	q_b[] = ( ram_block1a[7].portbdataout[0..0], ram_block1a[6].portbdataout[0..0], ram_block1a[5].portbdataout[0..0], ram_block1a[4].portbdataout[0..0], ram_block1a[3].portbdataout[0..0], ram_block1a[2].portbdataout[0..0], ram_block1a[1].portbdataout[0..0], ram_block1a[0].portbdataout[0..0]);
END;
--VALID FILE