proj_top.map.qmsg

这是一个FPGA的BCD码编码器设计.编译后可以下载到ALTEA的器件中仿真.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 02 21:11:01 2005 " "Info: Processing started: Wed Mar 02 21:11:01 2005" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --lower_priority --import_settings_files=on --export_settings_files=off example_proj -c proj_top " "Info: Command: quartus_map --lower_priority --import_settings_files=on --export_settings_files=off example_proj -c proj_top" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "proj_top.v 1 1 " "Info: Using design file proj_top.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 proj_top " "Info: Found entity 1: proj_top" {  } { { "C:/qdesigns/example_proj/proj_top.v" "proj_top" "" { Text "C:/qdesigns/example_proj/proj_top.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus/libraries/megafunctions/lpm_ram_dp.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file ../../quartus/libraries/megafunctions/lpm_ram_dp.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_ram_dp " "Info: Found entity 1: lpm_ram_dp" {  } { { "c:/quartus/libraries/megafunctions/lpm_ram_dp.tdf" "lpm_ram_dp" "" { Text "c:/quartus/libraries/megafunctions/lpm_ram_dp.tdf" 56 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus/libraries/megafunctions/altdpram.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file ../../quartus/libraries/megafunctions/altdpram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altdpram " "Info: Found entity 1: altdpram" {  } { { "c:/quartus/libraries/megafunctions/altdpram.tdf" "altdpram" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 170 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "34 " "Info: Implemented 34 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "18 " "Info: Implemented 18 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 02 21:11:02 2005 " "Info: Processing ended: Wed Mar 02 21:11:02 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}