proj_top_hier_info

这是一个FPGA的BCD码编码器设计.编译后可以下载到ALTEA的器件中仿真.

|proj_top
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
wraddress[0] => wraddress[0]~3.IN1
wraddress[1] => wraddress[1]~2.IN1
wraddress[2] => wraddress[2]~1.IN1
wraddress[3] => wraddress[3]~0.IN1
rdaddress[0] => rdaddress[0]~3.IN1
rdaddress[1] => rdaddress[1]~2.IN1
rdaddress[2] => rdaddress[2]~1.IN1
rdaddress[3] => rdaddress[3]~0.IN1
wren => wren~0.IN1
clock => clock~0.IN2
q[0] <= lpm_ram_dp:lpm_ram_dp_component.q
q[1] <= lpm_ram_dp:lpm_ram_dp_component.q
q[2] <= lpm_ram_dp:lpm_ram_dp_component.q
q[3] <= lpm_ram_dp:lpm_ram_dp_component.q
q[4] <= lpm_ram_dp:lpm_ram_dp_component.q
q[5] <= lpm_ram_dp:lpm_ram_dp_component.q
q[6] <= lpm_ram_dp:lpm_ram_dp_component.q
q[7] <= lpm_ram_dp:lpm_ram_dp_component.q


|proj_top|lpm_ram_dp:lpm_ram_dp_component
data[0] => altdpram:sram.data[0]
data[1] => altdpram:sram.data[1]
data[2] => altdpram:sram.data[2]
data[3] => altdpram:sram.data[3]
data[4] => altdpram:sram.data[4]
data[5] => altdpram:sram.data[5]
data[6] => altdpram:sram.data[6]
data[7] => altdpram:sram.data[7]
rdaddress[0] => altdpram:sram.rdaddress[0]
rdaddress[1] => altdpram:sram.rdaddress[1]
rdaddress[2] => altdpram:sram.rdaddress[2]
rdaddress[3] => altdpram:sram.rdaddress[3]
wraddress[0] => altdpram:sram.wraddress[0]
wraddress[1] => altdpram:sram.wraddress[1]
wraddress[2] => altdpram:sram.wraddress[2]
wraddress[3] => altdpram:sram.wraddress[3]
rdclock => altdpram:sram.outclock
wrclock => altdpram:sram.inclock
wren => altdpram:sram.wren
q[0] <= altdpram:sram.q[0]
q[1] <= altdpram:sram.q[1]
q[2] <= altdpram:sram.q[2]
q[3] <= altdpram:sram.q[3]
q[4] <= altdpram:sram.q[4]
q[5] <= altdpram:sram.q[5]
q[6] <= altdpram:sram.q[6]
q[7] <= altdpram:sram.q[7]


|proj_top|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram
wren => segment[0][7].WE
wren => segment[0][6].WE
wren => segment[0][5].WE
wren => segment[0][4].WE
wren => segment[0][3].WE
wren => segment[0][2].WE
wren => segment[0][1].WE
wren => segment[0][0].WE
data[0] => segment[0][0].DATAIN
data[1] => segment[0][1].DATAIN
data[2] => segment[0][2].DATAIN
data[3] => segment[0][3].DATAIN
data[4] => segment[0][4].DATAIN
data[5] => segment[0][5].DATAIN
data[6] => segment[0][6].DATAIN
data[7] => segment[0][7].DATAIN
wraddress[0] => segment[0][7].WADDR
wraddress[0] => segment[0][6].WADDR
wraddress[0] => segment[0][5].WADDR
wraddress[0] => segment[0][4].WADDR
wraddress[0] => segment[0][3].WADDR
wraddress[0] => segment[0][2].WADDR
wraddress[0] => segment[0][1].WADDR
wraddress[0] => segment[0][0].WADDR
wraddress[1] => segment[0][7].WADDR1
wraddress[1] => segment[0][6].WADDR1
wraddress[1] => segment[0][5].WADDR1
wraddress[1] => segment[0][4].WADDR1
wraddress[1] => segment[0][3].WADDR1
wraddress[1] => segment[0][2].WADDR1
wraddress[1] => segment[0][1].WADDR1
wraddress[1] => segment[0][0].WADDR1
wraddress[2] => segment[0][7].WADDR2
wraddress[2] => segment[0][6].WADDR2
wraddress[2] => segment[0][5].WADDR2
wraddress[2] => segment[0][4].WADDR2
wraddress[2] => segment[0][3].WADDR2
wraddress[2] => segment[0][2].WADDR2
wraddress[2] => segment[0][1].WADDR2
wraddress[2] => segment[0][0].WADDR2
wraddress[3] => segment[0][7].WADDR3
wraddress[3] => segment[0][6].WADDR3
wraddress[3] => segment[0][5].WADDR3
wraddress[3] => segment[0][4].WADDR3
wraddress[3] => segment[0][3].WADDR3
wraddress[3] => segment[0][2].WADDR3
wraddress[3] => segment[0][1].WADDR3
wraddress[3] => segment[0][0].WADDR3
inclock => segment[0][7].CLK0
inclock => segment[0][6].CLK0
inclock => segment[0][5].CLK0
inclock => segment[0][4].CLK0
inclock => segment[0][3].CLK0
inclock => segment[0][2].CLK0
inclock => segment[0][1].CLK0
inclock => segment[0][0].CLK0
rden => segment[0][7].RE
rden => segment[0][6].RE
rden => segment[0][5].RE
rden => segment[0][4].RE
rden => segment[0][3].RE
rden => segment[0][2].RE
rden => segment[0][1].RE
rden => segment[0][0].RE
rdaddress[0] => segment[0][7].RADDR
rdaddress[0] => segment[0][6].RADDR
rdaddress[0] => segment[0][5].RADDR
rdaddress[0] => segment[0][4].RADDR
rdaddress[0] => segment[0][3].RADDR
rdaddress[0] => segment[0][2].RADDR
rdaddress[0] => segment[0][1].RADDR
rdaddress[0] => segment[0][0].RADDR
rdaddress[1] => segment[0][7].RADDR1
rdaddress[1] => segment[0][6].RADDR1
rdaddress[1] => segment[0][5].RADDR1
rdaddress[1] => segment[0][4].RADDR1
rdaddress[1] => segment[0][3].RADDR1
rdaddress[1] => segment[0][2].RADDR1
rdaddress[1] => segment[0][1].RADDR1
rdaddress[1] => segment[0][0].RADDR1
rdaddress[2] => segment[0][7].RADDR2
rdaddress[2] => segment[0][6].RADDR2
rdaddress[2] => segment[0][5].RADDR2
rdaddress[2] => segment[0][4].RADDR2
rdaddress[2] => segment[0][3].RADDR2
rdaddress[2] => segment[0][2].RADDR2
rdaddress[2] => segment[0][1].RADDR2
rdaddress[2] => segment[0][0].RADDR2
rdaddress[3] => segment[0][7].RADDR3
rdaddress[3] => segment[0][6].RADDR3
rdaddress[3] => segment[0][5].RADDR3
rdaddress[3] => segment[0][4].RADDR3
rdaddress[3] => segment[0][3].RADDR3
rdaddress[3] => segment[0][2].RADDR3
rdaddress[3] => segment[0][1].RADDR3
rdaddress[3] => segment[0][0].RADDR3
outclock => segment[0][7].CLK1
outclock => segment[0][6].CLK1
outclock => segment[0][5].CLK1
outclock => segment[0][4].CLK1
outclock => segment[0][3].CLK1
outclock => segment[0][2].CLK1
outclock => segment[0][1].CLK1
outclock => segment[0][0].CLK1
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT
q[4] <= segment[0][4].DATAOUT
q[5] <= segment[0][5].DATAOUT
q[6] <= segment[0][6].DATAOUT
q[7] <= segment[0][7].DATAOUT