proj_top.tan.qmsg

这是一个FPGA的BCD码编码器设计.编译后可以下载到ALTEA的器件中仿真.

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clock q\[6\] lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[6\] 7.000 ns memory " "Info: Minimum tco from clock clock to destination pin q\[6\] through memory lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[6\] is 7.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.500 ns + Shortest memory " "Info: + Shortest clock path from clock clock to source memory is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clock 1 CLK Pin_55 96 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = Pin_55; Fanout = 96; CLK Node = 'clock'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "C:/qdesigns/example_proj/proj_top.v" "" "" { Text "C:/qdesigns/example_proj/proj_top.v" 54 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[6\] 2 MEM EC10_F 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = EC10_F; Fanout = 1; MEM Node = 'lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[6\]'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "0.200 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "1.500 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } { { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.200 ns + Shortest memory pin " "Info: + Shortest memory to pin delay is 5.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[6\] 1 MEM EC10_F 1 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = EC10_F; Fanout = 1; MEM Node = 'lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[6\]'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "" { lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(3.800 ns) 5.200 ns q\[6\] 2 PIN Pin_81 0 " "Info: 2: + IC(0.900 ns) + CELL(3.800 ns) = 5.200 ns; Loc. = Pin_81; Fanout = 0; PIN Node = 'q\[6\]'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "4.700 ns" { lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6] q[6] } "NODE_NAME" } } } { "C:/qdesigns/example_proj/proj_top.v" "" "" { Text "C:/qdesigns/example_proj/proj_top.v" 55 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.300 ns 82.69 % " "Info: Total cell delay = 4.300 ns ( 82.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.900 ns 17.31 % " "Info: Total interconnect delay = 0.900 ns ( 17.31 % )" {  } {  } 0}  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "5.200 ns" { lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6] q[6] } "NODE_NAME" } } }  } 0}  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "1.500 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6] } "NODE_NAME" } } } { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "5.200 ns" { lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6] q[6] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 02 21:11:30 2005 " "Info: Processing ended: Wed Mar 02 21:11:30 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}