proj_top.tan.qmsg

这是一个FPGA的BCD码编码器设计.编译后可以下载到ALTEA的器件中仿真.

{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clock " "Info: Assuming node clock is an undefined clock" {  } { { "C:/qdesigns/example_proj/proj_top.v" "" "" { Text "C:/qdesigns/example_proj/proj_top.v" 54 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock memory lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\]~reg_ra0 memory lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\] 227.27 MHz 4.4 ns Internal " "Info: Clock clock has Internal fmax of 227.27 MHz between source memory lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\]~reg_ra0 and destination memory lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\] (period= 4.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.200 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\]~reg_ra0 1 MEM EC11_F 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC11_F; Fanout = 1; MEM Node = 'lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\]~reg_ra0'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "" { lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0]~reg_ra0 } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.200 ns) 3.200 ns lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\]~mem_cell_ra0 2 MEM EC11_F 1 " "Info: 2: + IC(0.000 ns) + CELL(3.200 ns) = 3.200 ns; Loc. = EC11_F; Fanout = 1; MEM Node = 'lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\]~mem_cell_ra0'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "3.200 ns" { lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0]~reg_ra0 lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0]~mem_cell_ra0 } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.200 ns lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\] 3 MEM EC11_F 1 " "Info: 3: + IC(0.000 ns) + CELL(0.000 ns) = 3.200 ns; Loc. = EC11_F; Fanout = 1; MEM Node = 'lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\]'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "0.000 ns" { lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0]~mem_cell_ra0 lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns 100.00 % " "Info: Total cell delay = 3.200 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "3.200 ns" { lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0]~reg_ra0 lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0]~mem_cell_ra0 lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.500 ns + Shortest memory " "Info: + Shortest clock path from clock clock to destination memory is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clock 1 CLK Pin_55 96 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = Pin_55; Fanout = 96; CLK Node = 'clock'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "C:/qdesigns/example_proj/proj_top.v" "" "" { Text "C:/qdesigns/example_proj/proj_top.v" 54 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\] 2 MEM EC11_F 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = EC11_F; Fanout = 1; MEM Node = 'lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\]'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "0.200 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "1.500 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.500 ns - Longest memory " "Info: - Longest clock path from clock clock to source memory is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clock 1 CLK Pin_55 96 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = Pin_55; Fanout = 96; CLK Node = 'clock'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "C:/qdesigns/example_proj/proj_top.v" "" "" { Text "C:/qdesigns/example_proj/proj_top.v" 54 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\]~reg_ra0 2 MEM EC11_F 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = EC11_F; Fanout = 1; MEM Node = 'lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\]~reg_ra0'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "0.200 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0]~reg_ra0 } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "1.500 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0]~reg_ra0 } "NODE_NAME" } } }  } 0}  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "1.500 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0] } "NODE_NAME" } } } { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "1.500 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0]~reg_ra0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } { { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.900 ns + " "Info: + Micro setup delay of destination is 0.900 ns" {  } { { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0}  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "3.200 ns" { lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0]~reg_ra0 lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0]~mem_cell_ra0 lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0] } "NODE_NAME" } } } { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "1.500 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0] } "NODE_NAME" } } } { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "1.500 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0]~reg_ra0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[3\]~reg_in data\[3\] clock 4.600 ns memory " "Info: tsu for memory lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[3\]~reg_in (data pin = data\[3\], clock pin = clock) is 4.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.200 ns + Longest pin memory " "Info: + Longest pin to memory delay is 5.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns data\[3\] 1 PIN Pin_114 1 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_114; Fanout = 1; PIN Node = 'data\[3\]'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "" { data[3] } "NODE_NAME" } } } { "C:/qdesigns/example_proj/proj_top.v" "" "" { Text "C:/qdesigns/example_proj/proj_top.v" 50 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(0.600 ns) 5.200 ns lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[3\]~reg_in 2 MEM EC6_F 1 " "Info: 2: + IC(1.800 ns) + CELL(0.600 ns) = 5.200 ns; Loc. = EC6_F; Fanout = 1; MEM Node = 'lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[3\]~reg_in'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "2.400 ns" { data[3] lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[3]~reg_in } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 65.38 % " "Info: Total cell delay = 3.400 ns ( 65.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns 34.62 % " "Info: Total interconnect delay = 1.800 ns ( 34.62 % )" {  } {  } 0}  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "5.200 ns" { data[3] lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[3]~reg_in } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.900 ns + " "Info: + Micro setup delay of destination is 0.900 ns" {  } { { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.500 ns - Shortest memory " "Info: - Shortest clock path from clock clock to destination memory is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clock 1 CLK Pin_55 96 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = Pin_55; Fanout = 96; CLK Node = 'clock'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "C:/qdesigns/example_proj/proj_top.v" "" "" { Text "C:/qdesigns/example_proj/proj_top.v" 54 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[3\]~reg_in 2 MEM EC6_F 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = EC6_F; Fanout = 1; MEM Node = 'lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[3\]~reg_in'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "0.200 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[3]~reg_in } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "1.500 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[3]~reg_in } "NODE_NAME" } } }  } 0}  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "5.200 ns" { data[3] lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[3]~reg_in } "NODE_NAME" } } } { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "1.500 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[3]~reg_in } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock q\[0\] lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\] 9.200 ns memory " "Info: tco from clock clock to destination pin q\[0\] through memory lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\] is 9.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.500 ns + Longest memory " "Info: + Longest clock path from clock clock to source memory is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clock 1 CLK Pin_55 96 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = Pin_55; Fanout = 96; CLK Node = 'clock'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "C:/qdesigns/example_proj/proj_top.v" "" "" { Text "C:/qdesigns/example_proj/proj_top.v" 54 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\] 2 MEM EC11_F 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = EC11_F; Fanout = 1; MEM Node = 'lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\]'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "0.200 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "1.500 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } { { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.400 ns + Longest memory pin " "Info: + Longest memory to pin delay is 7.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\] 1 MEM EC11_F 1 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = EC11_F; Fanout = 1; MEM Node = 'lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\]'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "" { lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(3.800 ns) 7.400 ns q\[0\] 2 PIN Pin_96 0 " "Info: 2: + IC(3.100 ns) + CELL(3.800 ns) = 7.400 ns; Loc. = Pin_96; Fanout = 0; PIN Node = 'q\[0\]'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "6.900 ns" { lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0] q[0] } "NODE_NAME" } } } { "C:/qdesigns/example_proj/proj_top.v" "" "" { Text "C:/qdesigns/example_proj/proj_top.v" 55 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.300 ns 58.11 % " "Info: Total cell delay = 4.300 ns ( 58.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns 41.89 % " "Info: Total interconnect delay = 3.100 ns ( 41.89 % )" {  } {  } 0}  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "7.400 ns" { lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0] q[0] } "NODE_NAME" } } }  } 0}  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "1.500 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0] } "NODE_NAME" } } } { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "7.400 ns" { lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0] q[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[7\]~reg_we0 wren clock -0.600 ns memory " "Info: th for memory lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[7\]~reg_we0 (data pin = wren, clock pin = clock) is -0.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.500 ns + Longest memory " "Info: + Longest clock path from clock clock to destination memory is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clock 1 CLK Pin_55 96 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = Pin_55; Fanout = 96; CLK Node = 'clock'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "C:/qdesigns/example_proj/proj_top.v" "" "" { Text "C:/qdesigns/example_proj/proj_top.v" 54 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[7\]~reg_we0 2 MEM EC8_F 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = EC8_F; Fanout = 1; MEM Node = 'lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[7\]~reg_we0'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "0.200 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[7]~reg_we0 } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "1.500 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[7]~reg_we0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.400 ns + " "Info: + Micro hold delay of destination is 0.400 ns" {  } { { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.500 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 2.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns wren 1 PIN Pin_54 8 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = Pin_54; Fanout = 8; PIN Node = 'wren'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "" { wren } "NODE_NAME" } } } { "C:/qdesigns/example_proj/proj_top.v" "" "" { Text "C:/qdesigns/example_proj/proj_top.v" 53 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.400 ns) 2.500 ns lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[7\]~reg_we0 2 MEM EC8_F 1 " "Info: 2: + IC(0.800 ns) + CELL(0.400 ns) = 2.500 ns; Loc. = EC8_F; Fanout = 1; MEM Node = 'lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[7\]~reg_we0'" {  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "1.200 ns" { wren lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[7]~reg_we0 } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.700 ns 68.00 % " "Info: Total cell delay = 1.700 ns ( 68.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 32.00 % " "Info: Total interconnect delay = 0.800 ns ( 32.00 % )" {  } {  } 0}  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "2.500 ns" { wren lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[7]~reg_we0 } "NODE_NAME" } } }  } 0}  } { { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "1.500 ns" { clock lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[7]~reg_we0 } "NODE_NAME" } } } { "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" "" "" { Report "C:/qdesigns/example_proj/db/proj_top_cmp.qrpt" Compiler "proj_top" "UNKNOWN" "V1" "C:/qdesigns/example_proj/db/example_proj.quartus_db" { Floorplan "" "" "2.500 ns" { wren lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[7]~reg_we0 } "NODE_NAME" } } }  } 0}