clock.vhd

关于基于fpga的

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock is
    Port ( 	clk	:in std_logic;
			clk_1us,clk_5ms,clk_500ms,clk_1s	:out std_logic);
end clock;

architecture behavioral of clock is
signal	cnt12,cnt20k,cnt50	:integer	:=0;
signal	tmp1,tmp2,tmp3,tmp4,tmp4dly1,tmp4dly2	:std_logic	:='0';
begin
	process(clk)
	begin
		if clk'event and clk='1' then
			if cnt12=7 then	cnt12<=0;	tmp1<=not tmp1;
			else	cnt12<=cnt12 + 1;
		   	end if;
		end if;
	end process;
	clk_1us<=tmp1;
	process(tmp1)
	begin
		if tmp1'event and tmp1='1' then
			if cnt20k=2499	then	cnt20k<=0;	tmp2<=not tmp2;
			else	cnt20k<=cnt20k + 1;
			end if;
		end if;
	end process;
	clk_5ms<=tmp2;
	process(tmp2)
	begin
		if tmp2'event and tmp2='1' then
			if cnt50=49 then 	cnt50<=0;	tmp3<=not tmp3;
			else	cnt50<=cnt50 + 1;
			end if;
		end if;
	end process;
	clk_500ms<=tmp3;
	process(tmp3)
	begin
		if tmp3'event and tmp3='1' then
			tmp4<=not tmp4;
		end if;
	end process;

	process(tmp1,tmp4)
	begin
		if tmp1'event and tmp1='1' then
			tmp4dly1<=tmp4;
			tmp4dly2<=tmp4dly1;
		end if;
	end process;
	clk_1s<=not tmp4dly1 and tmp4dly2;	--Generate one shot
end behavioral;							--for clk_1s