scaladder.vhd

算术处理器的VERILOG hdl的源代码

-------------------------------------------------------------------------------
-- Title      : Scaling adder
-- Project    : Arithmetic blocks
-------------------------------------------------------------------------------
-- File        : ScalAdder.VHD
-- Author      : Jamil Khatib  
-- Organization: OpenIPCore Project
-- Created     : 2001/04/17
-- Last update : 2001/04/17
-- Platform    : 
-- Simulators  : Modelsim 5.3XE / Windows98
-- Synthesizers: Leonardo / WindowsNT
-- Target      : 
-- Dependency  : 
-------------------------------------------------------------------------------
-- Description: Scaling Adder
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Jamil Khatib
-- 
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it under the terms of the Openip General Public
-- License as it is going to be published by the OpenIPCore Organization and
-- any coming versions of this license.
-- You can check the draft license at
-- http://www.openip.org/oc/license.html

-------------------------------------------------------------------------------
-- Revisions  :
-- Revision Number :   1
-- Version         :   0.1
-- Date            :   17th Apr 2001
-- Modifier        :   Jamil Khatib ([e-mail])
-- Desccription    :   Created
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity ScaleAddr is

  generic (
    OPSIZE : integer := 8);             -- Operand size


  port (
    Op  : in  std_logic_vector(OPSIZE - 1 downto 0);  -- Operand
    Res : out std_logic_vector(OPSIZE -1 downto 0);   -- Result

    Overflow : out std_logic;           -- Overflow
    ValidOut : out std_logic;           -- valid output active high
    clk      : in  std_logic;           -- system clock positive edge
    rst_n    : in  std_logic);          -- system reset active low

end ScaleAddr;



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

architecture behavior of ScaleAddr is


begin  -- behavior

  -- purpose: calculates MAC using serial approach
  -- type   : sequential
  -- inputs : clk    positive edge
  --          rst_n  active low
  -- outputs: 
  mac : process (clk, rst_n)


    variable tmpres   : std_logic_vector(OPSIZE - 1 downto 0);
                                                        -- Temporary result
    variable count    : integer range 0 to (OPSIZE-1);  -- counter
    variable validvar : std_logic;                      -- ValidOut variable
    variable optmp    : std_logic_vector(OPSIZE-1 downto 0);
                                                        -- input register of Operand

    variable overflow_var : std_logic;  -- Over Flow variable

  begin  -- process mac

    if rst_n = '0' then                 -- asynchronous reset (active low)

      ValidOut     <= '1';
      Res          <= (others => '0');
      validvar     := '1';
      tmpres       := (others => '0');
      count        := 0;
      overflow_var := '0';
      optmp        := (others => '0');

    elsif clk'event and clk = '1' then  -- rising clock edge

      if validvar = '1' then

        validvar     := '0';
        tmpres       := (others => '0');
        Overflow_var := '0';
        Optmp := Op;                    -- Load new Operand
      end if;
      
     

      if count = (OPSIZE -1) then

        validvar := '1';
        count := 0;
        
      else
        
        count := count + 1;
        
      end if;

      overflow_var := overflow_var or tmpres(OPSIZE-1);

      tmpres := tmpres(OPSIZE -2 downto 0 ) & '0';

      tmpres := tmpres + Optmp;

      Res <= tmpres;

     

    end if;

    ValidOut <= validvar;
    Overflow <= overflow_var;
    
  end process mac;

end behavior;