📄 decoder.v
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src_sel2 = `ASS_ZERO; alu_op = `ALU_ADD; wr = 1'b1; psw_set = `PS_NOT; cy_sel = `CY_1; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_DC; src_sel3 = `AS3_DC; comp_sel = `CSS_DC; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `INC_D : begin ram_rd_sel = `RRS_D; ram_wr_sel = `RWS_D; src_sel1 = `ASS_RAM; src_sel2 = `ASS_ZERO; alu_op = `ALU_ADD; wr = 1'b1; psw_set = `PS_NOT; cy_sel = `CY_1; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_DC; src_sel3 = `AS3_DC; comp_sel = `CSS_DC; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `INC_DP : begin ram_rd_sel = `RRS_D; ram_wr_sel = `RWS_DPTR; src_sel1 = `ASS_RAM; src_sel2 = `ASS_ZERO; alu_op = `ALU_ADD; wr = 1'b1; psw_set = `PS_NOT; cy_sel = `CY_1; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = 2'bxx; src_sel3 = `AS3_DP; comp_sel = `CSS_DC; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `JB : begin ram_rd_sel = `RRS_D; ram_wr_sel = `RWS_DC; src_sel1 = `ASS_IMM; src_sel2 = `ASS_OP2; alu_op = `ALU_PCS; wr = 1'b0; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_OP3; src_sel3 = `AS3_PC; comp_sel = `CSS_BIT; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `JBC :begin ram_rd_sel = `RRS_D; ram_wr_sel = `RWS_DC; src_sel1 = `ASS_IMM; src_sel2 = `ASS_OP2; alu_op = `ALU_PCS; wr = 1'b0; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_OP3; src_sel3 = `AS3_PC; comp_sel = `CSS_BIT; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `JC : begin ram_rd_sel = `RRS_DC; ram_wr_sel = `RWS_DC; src_sel1 = `ASS_IMM; src_sel2 = `ASS_OP2; alu_op = `ALU_PCS; wr = 1'b0; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_OP2; src_sel3 = `AS3_PC; comp_sel = `CSS_CY; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `JMP : begin ram_rd_sel = `RRS_D; ram_wr_sel = `RWS_DC; src_sel1 = `ASS_ACC; src_sel2 = `ASS_RAM; alu_op = `ALU_ADD; wr = 1'b0; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_DC; src_sel3 = `AS3_DP; comp_sel = `CSS_BIT; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `JNB : begin ram_rd_sel = `RRS_D; ram_wr_sel = `RWS_DC; src_sel1 = `ASS_IMM; src_sel2 = `ASS_OP2; alu_op = `ALU_PCS; wr = 1'b0; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_OP3; src_sel3 = `AS3_PC; comp_sel = `CSS_BIT; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `JNC : begin ram_rd_sel = `RRS_DC; ram_wr_sel = `RWS_DC; src_sel1 = `ASS_IMM; src_sel2 = `ASS_OP2; alu_op = `ALU_PCS; wr = 1'b0; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_OP2; src_sel3 = `AS3_PC; comp_sel = `CSS_CY; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `JNZ :begin ram_rd_sel = `RRS_DC; ram_wr_sel = `RWS_DC; src_sel1 = `ASS_IMM; src_sel2 = `ASS_OP2; alu_op = `ALU_PCS; wr = 1'b0; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_OP2; src_sel3 = `AS3_PC; comp_sel = `CSS_AZ; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `JZ : begin ram_rd_sel = `RRS_DC; ram_wr_sel = `RWS_DC; src_sel1 = `ASS_IMM; src_sel2 = `ASS_OP2; alu_op = `ALU_PCS; wr = 1'b0; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_OP2; src_sel3 = `AS3_PC; comp_sel = `CSS_AZ; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `LCALL :begin ram_rd_sel = 2'bxx; ram_wr_sel = `RWS_SP; src_sel1 = `ASS_IMM; src_sel2 = 2'bxx; alu_op = `ALU_NOP; imm_sel = `IDS_PCL; wr = 1'b1; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_Y; pc_sel = `PIS_I16; src_sel3 = `AS3_DC; comp_sel = `CSS_DC; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `LJMP : begin ram_rd_sel = 2'bxx; ram_wr_sel = 2'bxx; src_sel1 = 2'bxx; src_sel2 = 2'bxx; alu_op = 4'bxxxx; imm_sel = 2'bxx; wr = 1'b0; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_Y; pc_sel = `PIS_I16; src_sel3 = `AS3_DC; comp_sel = `CSS_DC; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `MOV_D : begin ram_rd_sel = `RRS_D; ram_wr_sel = `RWS_ACC; src_sel1 = `ASS_RAM; src_sel2 = `ASS_DC; alu_op = `ALU_NOP; wr = 1'b1; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_DC; src_sel3 = `AS3_DC; comp_sel = `CSS_DC; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `MOV_C : begin ram_rd_sel = `RRS_DC; ram_wr_sel = `RWS_ACC; src_sel1 = `ASS_IMM; src_sel2 = `ASS_DC; alu_op = `ALU_NOP; wr = 1'b1; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_OP2; src_sel3 = `AS3_DC; comp_sel = `CSS_DC; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `MOV_DA : begin ram_rd_sel = `RRS_DC; ram_wr_sel = `RWS_D; src_sel1 = `ASS_ACC; src_sel2 = `ASS_DC; alu_op = `ALU_NOP; wr = 1'b1; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_DC; src_sel3 = `AS3_DC; comp_sel = `CSS_DC; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `MOV_DD : begin ram_rd_sel = `RRS_D; ram_wr_sel = `RWS_D3; src_sel1 = `ASS_RAM; src_sel2 = `ASS_DC; alu_op = `ALU_NOP; wr = 1'b1; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_OP2; src_sel3 = `AS3_DC; comp_sel = `CSS_DC; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `MOV_CD : begin ram_rd_sel = `RRS_DC; ram_wr_sel = `RWS_D; src_sel1 = `ASS_IMM; src_sel2 = `ASS_DC; alu_op = `ALU_NOP; wr = 1'b1; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_OP3; src_sel3 = `AS3_DC; comp_sel = `CSS_DC; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `MOV_BC : begin ram_rd_sel = `RRS_D; ram_wr_sel = `RWS_DC; src_sel1 = `ASS_DC; src_sel2 = `ASS_DC; alu_op = `ALU_NOP; wr = 1'b0; psw_set = `PS_CY; cy_sel = `CY_RAM; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_DC; src_sel3 = `AS3_DC; comp_sel = `CSS_DC; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `MOV_CB : begin ram_rd_sel = `RRS_DC; ram_wr_sel = `RWS_D; src_sel1 = `ASS_DC; src_sel2 = `ASS_DC; alu_op = `ALU_NOP; wr = 1'b1; psw_set = `PS_NOT; cy_sel = `CY_PSW; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_OP3; src_sel3 = `AS3_DC; comp_sel = `CSS_DC; wr_bit = 1'b1; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `MOV_DP : begin ram_rd_sel = `RRS_DC; ram_wr_sel = `RWS_DPTR; src_sel1 = `ASS_IMM; src_sel2 = `ASS_OP2; alu_op = `ALU_NOP; wr = 1'b1; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_OP3; src_sel3 = `AS3_DC; comp_sel = `CSS_DC; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `MOVC_DP :begin ram_rd_sel = `RRS_D; ram_wr_sel = `RWS_DC; src_sel1 = `ASS_ACC; src_sel2 = `ASS_RAM; alu_op = `ALU_ADD; wr = 1'b0; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = 2'bxx; src_sel3 = `AS3_DP; comp_sel = `CSS_DC; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `MOVC_PC : begin ram_rd_sel = `RRS_DC; ram_wr_sel = `RWS_DC; src_sel1 = `ASS_ACC; src_sel2 = `ASS_OP2; alu_op = `ALU_ADD; wr = 1'b0; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = 2'bxx; src_sel3 = `AS3_DP; comp_sel = `CSS_DC; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DC; end `MOVX_PA : begin ram_rd_sel = `RRS_DC; ram_wr_sel = `RWS_ACC; src_sel1 = `ASS_XRAM; src_sel2 = `ASS_DC; alu_op = `ALU_NOP; wr = 1'b1; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `PCW_N; pc_sel = `PIS_DC; imm_sel = `IDS_OP2; src_sel3 = `AS3_DC; comp_sel = `CSS_DC; wr_bit = 1'b0; wad2 = `WAD_N; rom_addr_sel = `RAS_PC; ext_addr_sel = `EAS_DPTR; end `MOVX_AP : begin ram_rd_sel = `RRS_DC; ram_wr_sel = `RWS_DC; src_sel1 = `ASS_XRAM; src_sel2 = `ASS_DC; alu_op = `ALU_NOP; wr = 1'b0; psw_set = `PS_NOT; cy_sel = `CY_0; pc_wr = `⌨️ 快捷键说明
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