f_testbench.v

新型串并架构的高速FIR滤波器,对研究VHDL实现FIR的朋友有用处

`timescale 1ns/1ns
module F_testbench();

parameter	Clk_period=100;
parameter	Mult_patio=4;
parameter	Reset_time=Mult_patio*Clk_period;
parameter	word_size=12;

reg[word_size-1:0]	data_mem[1:0];
reg[word_size-1:0]	D_save;
reg		D_Com;

reg			clk,
			rst;
wire[15:0]	D_out;

integer		j,i;
			
Filter_ws  filter(
            .clk(clk),
            .D_Com(D_Com),
            .reset(rst),
            .filter_in(D_save),
            .filter_out(D_out)
            );

initial
fork
    data_mem[0]=1;
	data_mem[1]=0;
   	i=0;
	D_Com=0;
join

always @(posedge clk)begin//激励数据出
	if(rst == 1'b0)begin
		#2 D_Com=1;
		D_save=data_mem[i];//数据循环输出		 
		i=1'b1;
		@(posedge clk)
			#2 D_Com=0;	
		repeat(19)
			 @(posedge clk);
	end
end
			
initial
begin
	rst=1'b1;
	#Reset_time rst=1'b0;
end

initial
begin
	clk=1'b0;
	forever
		#(Clk_period/2) clk=~clk;
end

initial
begin
	$monitor($time,,,"D_out=%d",D_out);
end

endmodule