filter_ws.v

新型串并架构的高速FIR滤波器,对研究VHDL实现FIR的朋友有用处

module Filter_ws 
               (
                clk,
                D_Com,
                reset,
                filter_in,
                filter_out,
				output_register//仿真用，仿真验证完毕后删除
                );
input   	clk; 
input  		D_Com; 
input  		reset; 
input[D_in_width-1:0] 	filter_in; 
output[D_out_width-1:0] filter_out;
output[D_in_width+coeff_size+12:0]	output_register; 

parameter	D_in_width = 12;
parameter 	D_out_width = 16;
parameter 	ptr_ADD = 3;
parameter 	ptr_MAC = 2;
parameter 	pipeline_longer = 64;
parameter	M_Block_size = 4;
parameter	Work_way_num = 8; 
parameter	coeff_size = 16;

parameter 	coeff1  = -89;
parameter 	coeff2  = -562;
parameter 	coeff3  = -1174;
parameter 	coeff4  = -1486;
parameter 	coeff5  = -1034;
parameter 	coeff6  = -38;
parameter 	coeff7  = 674;
parameter 	coeff8  = 493;
parameter 	coeff9  = -235;
parameter 	coeff10 = -572; 
parameter 	coeff11 = -118;
parameter 	coeff12 = 481;
parameter 	coeff13 = 389;
parameter 	coeff14 = -275;
parameter 	coeff15 = -565;
parameter 	coeff16 = -22;
parameter 	coeff17 = 608;
parameter 	coeff18 = 374;
parameter 	coeff19 = -473;
parameter 	coeff20 = -704;
parameter 	coeff21 = 140; 
parameter 	coeff22 = 919; 
parameter 	coeff23 = 382; 
parameter 	coeff24 = -899; 
parameter 	coeff25 = -1032; 
parameter 	coeff26 = 520; 
parameter 	coeff27 = 1716; 
parameter 	coeff28 = 393; 
parameter 	coeff29 = -2319; 
parameter 	coeff30 = -2346; 
parameter 	coeff31 = 2732; 
parameter 	coeff32 = 10033;
parameter 	coeff33 = 13505; 

parameter	state_size = 4;
parameter	S_0 = 4'b0001;
parameter	S_1 = 4'b0010;
parameter	S_2 = 4'b0100;
parameter	S_3 = 4'b1000;

reg[D_in_width:0]	D_in_save;
reg[D_in_width:0] 	delay_pipeline [pipeline_longer-1:0];

reg[D_in_width:0]	M41[M_Block_size-1:0];
reg[D_in_width:0]	M42[M_Block_size-1:0];
reg[D_in_width:0]	M43[M_Block_size-1:0];
reg[D_in_width:0]	M44[M_Block_size-1:0];
reg[D_in_width:0]	M45[M_Block_size-1:0];
reg[D_in_width:0]	M46[M_Block_size-1:0];
reg[D_in_width:0]	M47[M_Block_size-1:0];
reg[D_in_width:0]	M48[M_Block_size-1:0];
reg[ptr_MAC-1:0] 	MAC_ptr;
reg[coeff_size-1:0]	C41;
reg[coeff_size-1:0]	C42;
reg[coeff_size-1:0]	C43;
reg[coeff_size-1:0]	C44;
reg[coeff_size-1:0]	C45;
reg[coeff_size-1:0]	C46;
reg[coeff_size-1:0]	C47;
reg[coeff_size-1:0]	C48;
reg[coeff_size-1:0] C33;

reg[D_in_width+coeff_size+4:0]	ADD_er[Work_way_num-1:0];
reg[ptr_ADD-1:0]	ADD_ptr;
reg[D_in_width+coeff_size+12:0]	output_register;

reg[state_size-1:0]	next_state,
					state;
reg 				store,
					clear,
					MAC,
					ADD;

wire				MAC_Ok;
wire				ADD_Ok;
wire[D_in_width+coeff_size:0]	M41_W;
wire[D_in_width+coeff_size:0]	M42_W;
wire[D_in_width+coeff_size:0]	M43_W;
wire[D_in_width+coeff_size:0]	M44_W;
wire[D_in_width+coeff_size:0]	M45_W;
wire[D_in_width+coeff_size:0]	M46_W;
wire[D_in_width+coeff_size:0]	M47_W;
wire[D_in_width+coeff_size:0]	M48_W;
wire[D_in_width+coeff_size:0]	output_register_W;

integer 			i,j,k,m;	

assign filter_out = output_register[D_in_width+coeff_size+12:D_in_width+coeff_size-3];

always @(posedge clk)begin
	if(reset == 1'b1)
		D_in_save <= 0;
	else begin
		if (store == 1'b1)	
			D_in_save <= {filter_in[D_in_width-1],filter_in};//对输入的采样数据进行处理，
		//对负数使之为补码形式,这里假设进入的数据已经为补码形式，所以只进行符号扩展处理							
	end
end

always @(posedge clk)begin: Delay_Pipeline_process
	if (reset == 1'b1)
		for(i=0;i<64;i=i+1)
        	delay_pipeline[i] <= 0;
    else begin
        if (store == 1'b1) begin			
			delay_pipeline[0] <= D_in_save;
			//for(k=0;k<pipeline_longer;k=k+1)
			//	delay_pipeline[k+1] <= delay_pipeline[k];
			delay_pipeline[1]  <= delay_pipeline[0];
          	delay_pipeline[2]  <= delay_pipeline[1];
          	delay_pipeline[3]  <= delay_pipeline[2];
          	delay_pipeline[4]  <= delay_pipeline[3];
          	delay_pipeline[5]  <= delay_pipeline[4];
          	delay_pipeline[6]  <= delay_pipeline[5];
          	delay_pipeline[7]  <= delay_pipeline[6];
          	delay_pipeline[8]  <= delay_pipeline[7];
          	delay_pipeline[9]  <= delay_pipeline[8];
          	delay_pipeline[10] <= delay_pipeline[9];
          	delay_pipeline[11] <= delay_pipeline[10];
          	delay_pipeline[12] <= delay_pipeline[11];
          	delay_pipeline[13] <= delay_pipeline[12];
          	delay_pipeline[14] <= delay_pipeline[13];
          	delay_pipeline[15] <= delay_pipeline[14];
          	delay_pipeline[16] <= delay_pipeline[15];
          	delay_pipeline[17] <= delay_pipeline[16];
          	delay_pipeline[18] <= delay_pipeline[17];
          	delay_pipeline[19] <= delay_pipeline[18];
          	delay_pipeline[20] <= delay_pipeline[19];
          	delay_pipeline[21] <= delay_pipeline[20];
          	delay_pipeline[22] <= delay_pipeline[21];
          	delay_pipeline[23] <= delay_pipeline[22];
          	delay_pipeline[24] <= delay_pipeline[23];
          	delay_pipeline[25] <= delay_pipeline[24];
          	delay_pipeline[26] <= delay_pipeline[25];
          	delay_pipeline[27] <= delay_pipeline[26];
          	delay_pipeline[28] <= delay_pipeline[27];
          	delay_pipeline[29] <= delay_pipeline[28];
          	delay_pipeline[30] <= delay_pipeline[29];
          	delay_pipeline[31] <= delay_pipeline[30];
          	delay_pipeline[32] <= delay_pipeline[31];
          	delay_pipeline[33] <= delay_pipeline[32];
          	delay_pipeline[34] <= delay_pipeline[33];
          	delay_pipeline[35] <= delay_pipeline[34];
          	delay_pipeline[36] <= delay_pipeline[35];
          	delay_pipeline[37] <= delay_pipeline[36];
          	delay_pipeline[38] <= delay_pipeline[37];
          	delay_pipeline[39] <= delay_pipeline[38];
          	delay_pipeline[40] <= delay_pipeline[39];
          	delay_pipeline[41] <= delay_pipeline[40];
          	delay_pipeline[42] <= delay_pipeline[41];
          	delay_pipeline[43] <= delay_pipeline[42];
          	delay_pipeline[44] <= delay_pipeline[43];
          	delay_pipeline[45] <= delay_pipeline[44];
          	delay_pipeline[46] <= delay_pipeline[45];
          	delay_pipeline[47] <= delay_pipeline[46];
          	delay_pipeline[48] <= delay_pipeline[47];
          	delay_pipeline[49] <= delay_pipeline[48];
          	delay_pipeline[50] <= delay_pipeline[49];
          	delay_pipeline[51] <= delay_pipeline[50];
          	delay_pipeline[52] <= delay_pipeline[51];
          	delay_pipeline[53] <= delay_pipeline[52];
          	delay_pipeline[54] <= delay_pipeline[53];
          	delay_pipeline[55] <= delay_pipeline[54];
          	delay_pipeline[56] <= delay_pipeline[55];
          	delay_pipeline[57] <= delay_pipeline[56];
          	delay_pipeline[58] <= delay_pipeline[57];
          	delay_pipeline[59] <= delay_pipeline[58];
          	delay_pipeline[60] <= delay_pipeline[59];
          	delay_pipeline[61] <= delay_pipeline[60];
          	delay_pipeline[62] <= delay_pipeline[61];
          	delay_pipeline[63] <= delay_pipeline[62];
		end
    end
end 
always @(posedge clk)begin:Once_Add_process
	if (reset == 1'b1) begin
		for(j=0;j<=3;j=j+1)begin
        	M41[j] <= 0;
			M42[j] <= 0;
			M43[j] <= 0;
			M44[j] <= 0;
			M45[j] <= 0;
			M46[j] <= 0;
			M47[j] <= 0;
			M48[j] <= 0;
		end
    end
    else begin
        if (store == 1'b1) begin
			M41[0] <= D_in_save          + delay_pipeline[63];
			M41[1] <= delay_pipeline[0]  + delay_pipeline[62];
			M41[2] <= delay_pipeline[1]  + delay_pipeline[61];
			M41[3] <= delay_pipeline[2]  + delay_pipeline[60];
			M42[0] <= delay_pipeline[3]  + delay_pipeline[59];
			M42[1] <= delay_pipeline[4]  + delay_pipeline[58];
			M42[2] <= delay_pipeline[5]  + delay_pipeline[57];
			M42[3] <= delay_pipeline[6]  + delay_pipeline[56];
			M43[0] <= delay_pipeline[7]  + delay_pipeline[55];
			M43[1] <= delay_pipeline[8]  + delay_pipeline[54];
			M43[2] <= delay_pipeline[9]  + delay_pipeline[53];
			M43[3] <= delay_pipeline[10] + delay_pipeline[52];
			M44[0] <= delay_pipeline[11] + delay_pipeline[51];
			M44[1] <= delay_pipeline[12] + delay_pipeline[50];
			M44[2] <= delay_pipeline[13] + delay_pipeline[49];
			M44[3] <= delay_pipeline[14] + delay_pipeline[48];
			M45[0] <= delay_pipeline[15] + delay_pipeline[47];
			M45[1] <= delay_pipeline[16] + delay_pipeline[46];
			M45[2] <= delay_pipeline[17] + delay_pipeline[45];
			M45[3] <= delay_pipeline[18] + delay_pipeline[44];
			M46[0] <= delay_pipeline[19] + delay_pipeline[43];
			M46[1] <= delay_pipeline[20] + delay_pipeline[42];
			M46[2] <= delay_pipeline[21] + delay_pipeline[41];
			M46[3] <= delay_pipeline[22] + delay_pipeline[40];
			M47[0] <= delay_pipeline[23] + delay_pipeline[39];
			M47[1] <= delay_pipeline[24] + delay_pipeline[38];
			M47[2] <= delay_pipeline[25] + delay_pipeline[37];
			M47[3] <= delay_pipeline[26] + delay_pipeline[36];
			M48[0] <= delay_pipeline[27] + delay_pipeline[35];
			M48[1] <= delay_pipeline[28] + delay_pipeline[34];
			M48[2] <= delay_pipeline[29] + delay_pipeline[33];
			M48[3] <= delay_pipeline[30] + delay_pipeline[32];
		end
	end
end

always @(posedge clk)begin
	if(reset == 1'b1)
		state<=S_0;
	else
		state<=next_state;
end

always @(state or D_Com or MAC_Ok or ADD_Ok)begin
	store=0;
	clear=0;
	MAC=0;
	ADD=0;
	next_state=state;
	case(state)
		S_0:begin
			clear=1;
			next_state=S_1;
			end
		S_1:if(D_Com)begin
				store=1;
				next_state=S_2;
			end
		S_2:if(MAC_Ok)begin
				MAC=1;
				next_state=S_3;
			end
			else 
				MAC=1;
		S_3:if(ADD_Ok)begin
				ADD=1;
				next_state=S_0;
			end
			else
				ADD=1;
		default:next_state=S_0;
	endcase
end

mult_ws M_1(
		.dataa(M41[MAC_ptr]),
		.datab(C41),
		.result(M41_W)
		);
		
mult_ws M_2(
		.dataa(M42[MAC_ptr]),
		.datab(C42),
		.result(M42_W)
		);

mult_ws M_3(
		.dataa(M43[MAC_ptr]),
		.datab(C43),
		.result(M43_W)
		);

mult_ws M_4(
		.dataa(M44[MAC_ptr]),
		.datab(C44),
		.result(M44_W)
		);

mult_ws M_5(
		.dataa(M45[MAC_ptr]),
		.datab(C45),
		.result(M45_W)
		);

mult_ws M_6(
		.dataa(M46[MAC_ptr]),
		.datab(C46),
		.result(M46_W)
		);
		
mult_ws M_7(
		.dataa(M47[MAC_ptr]),
		.datab(C47),
		.result(M47_W)
		);

mult_ws M_8(
		.dataa(M48[MAC_ptr]),
		.datab(C48),
		.result(M48_W)
		);

assign	MAC_Ok = (MAC_ptr == (M_Block_size-1))?1'b1:1'b0;
assign  ADD_Ok = (ADD_ptr == (Work_way_num-1))?1'b1:1'b0;

always @(posedge clk)begin:MAC_process
	if(clear == 1'b1)begin
		for(m=0;m<Work_way_num;m=m+1)
			ADD_er[m] <= 0;
		MAC_ptr <= 0;
	end
	else begin
		if(MAC == 1'b1)begin
			ADD_er[0] <= ADD_er[0] + {{4{M41_W[D_in_width+coeff_size]}},M41_W};
			ADD_er[1] <= ADD_er[1] + {{4{M42_W[D_in_width+coeff_size]}},M42_W};
			ADD_er[2] <= ADD_er[2] + {{4{M43_W[D_in_width+coeff_size]}},M43_W};
			ADD_er[3] <= ADD_er[3] + {{4{M44_W[D_in_width+coeff_size]}},M44_W};
			ADD_er[4] <= ADD_er[4] + {{4{M45_W[D_in_width+coeff_size]}},M45_W};
			ADD_er[5] <= ADD_er[5] + {{4{M46_W[D_in_width+coeff_size]}},M46_W};
			ADD_er[6] <= ADD_er[6] + {{4{M47_W[D_in_width+coeff_size]}},M47_W};
			ADD_er[7] <= ADD_er[7] + {{4{M48_W[D_in_width+coeff_size]}},M48_W};
			MAC_ptr <= MAC_ptr+1;
		end
	end
end

always @(MAC_ptr)begin
	case(MAC_ptr)
		2'b00:C41 = coeff1;
		2'b01:C41 = coeff2;
		2'b10:C41 = coeff3;
		2'b11:C41 = coeff4;
	endcase
end

always @(MAC_ptr)begin
	case(MAC_ptr)
		2'b00:C42 = coeff5;
		2'b01:C42 = coeff6;
		2'b10:C42 = coeff7;
		2'b11:C42 = coeff8;
	endcase
end

always @(MAC_ptr)begin
	case(MAC_ptr)
		2'b00:C43 = coeff9;
		2'b01:C43 = coeff10;
		2'b10:C43 = coeff11;
		2'b11:C43 = coeff12;
	endcase
end

always @(MAC_ptr)begin
	case(MAC_ptr)
		2'b00:C44 = coeff13;
		2'b01:C44 = coeff14;
		2'b10:C44 = coeff15;
		2'b11:C44 = coeff16;
	endcase
end

always @(MAC_ptr)begin
	case(MAC_ptr)
		2'b00:C45 = coeff17;
		2'b01:C45 = coeff18;
		2'b10:C45 = coeff19;
		2'b11:C45 = coeff20;
	endcase
end

always @(MAC_ptr)begin
	case(MAC_ptr)
		2'b00:C46 = coeff21;
		2'b01:C46 = coeff22;
		2'b10:C46 = coeff23;
		2'b11:C46 = coeff24;
	endcase
end

always @(MAC_ptr)begin
	case(MAC_ptr)
		2'b00:C47 = coeff25;
		2'b01:C47 = coeff26;
		2'b10:C47 = coeff27;
		2'b11:C47 = coeff28;
	endcase
end

always @(MAC_ptr)begin
	case(MAC_ptr)
		2'b00:C48 = coeff29;
		2'b01:C48 = coeff30;
		2'b10:C48 = coeff31;
		2'b11:C48 = coeff32;
	endcase
end

always 
	C33 = coeff33;

mult_ws M_9(
		.dataa(delay_pipeline[31]),
		.datab(C33),
		.result(output_register_W)
		);

always @(posedge clk)begin:ADD_process
	if(store == 1'b1)begin
		output_register <= {{8{output_register_W[D_in_width+coeff_size]}},output_register_W};
		ADD_ptr <= 0;
	end
	else begin
		if(ADD == 1'b1)begin
			output_register <= output_register + ADD_er[ADD_ptr];
			ADD_ptr <= ADD_ptr+1;
		end
	end
end

endmodule  // filter

module mult_ws (
	dataa,
	datab,
	result);

	input	[12:0]  dataa;
	input	[15:0]  datab;
	output	[28:0]  result;

	wire [28:0] sub_wire0;
	wire [28:0] result = sub_wire0[28:0];

	lpm_mult	lpm_mult_component (
				.dataa (dataa),
				.datab (datab),
				.result (sub_wire0),
				.aclr (1'b0),
				.clken (1'b1),
				.clock (1'b0),
				.sum (1'b0));
	defparam
		lpm_mult_component.lpm_widtha = 13,
		lpm_mult_component.lpm_widthb = 16,
		lpm_mult_component.lpm_widthp = 29,
		lpm_mult_component.lpm_widths = 1,
		lpm_mult_component.lpm_type = "LPM_MULT",
		lpm_mult_component.lpm_representation = "SIGNED",
		lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5";
		
endmodule