system.h

这是一个基于NIOSII的俄罗斯方块游戏设计

/* system.h
 *
 * Machine generated for a CPU named "cpu" as defined in:
 * E:\12\educationdesign\nios32.ptf
 *
 * Generated: 2006-06-02 17:41:57.875
 *
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "nios32"
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "CYCLONE"
#define UP3_BOARD
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_CPU_FREQ 48000000
#define ALT_IRQ_BASE NULL

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "tiny"

#define NIOS2_ICACHE_SIZE 0
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE_LOG2 0
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x00800020
#define NIOS2_RESET_ADDR 0x00000000

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_TIMER
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_CFI_FLASH
#define __ALTERA_AVALON_DMA
#define __ALTERA_AVALON_SYSID
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __SRAM_UP3
#define __ALTERA_AVALON_TRI_STATE_BRIDGE
#define __VGA
#define __SLS_TRISTATE_16X2_CHARACTER_LCD

/*
 * boot_rom configuration
 *
 */

#define BOOT_ROM_NAME "/dev/boot_rom"
#define BOOT_ROM_TYPE "altera_avalon_onchip_memory2"
#define BOOT_ROM_BASE 0x00221000
#define BOOT_ROM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define BOOT_ROM_RAM_BLOCK_TYPE "M4K"
#define BOOT_ROM_GUI_RAM_BLOCK_TYPE "Automatic"
#define BOOT_ROM_WRITEABLE 0
#define BOOT_ROM_DUAL_PORT 0
#define BOOT_ROM_SIZE_VALUE 2
#define BOOT_ROM_SIZE_MULTIPLE 1024
#define BOOT_ROM_CONTENTS_INFO "QUARTUS_PROJECT_DIR/boot_rom.hex 1147356445"

/*
 * jtag_uart configuration
 *
 */

#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_BASE 0x00220060
#define JTAG_UART_IRQ 0
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_READ_CHAR_STREAM ""
#define JTAG_UART_SHOWASCII 1
#define JTAG_UART_READ_LE 0
#define JTAG_UART_WRITE_LE 0

/*
 * timer1 configuration
 *
 */

#define TIMER1_NAME "/dev/timer1"
#define TIMER1_TYPE "altera_avalon_timer"
#define TIMER1_BASE 0x00220020
#define TIMER1_IRQ 1
#define TIMER1_ALWAYS_RUN 0
#define TIMER1_FIXED_PERIOD 0
#define TIMER1_SNAPSHOT 1
#define TIMER1_PERIOD 1
#define TIMER1_PERIOD_UNITS "ms"
#define TIMER1_RESET_OUTPUT 0
#define TIMER1_TIMEOUT_PULSE_OUTPUT 0
#define TIMER1_MULT 0.001
#define TIMER1_FREQ 48000000

/*
 * button_pio configuration
 *
 */

#define BUTTON_PIO_NAME "/dev/button_pio"
#define BUTTON_PIO_TYPE "altera_avalon_pio"
#define BUTTON_PIO_BASE 0x00220010
#define BUTTON_PIO_IRQ 2
#define BUTTON_PIO_DO_TEST_BENCH_WIRING 0
#define BUTTON_PIO_DRIVEN_SIM_VALUE 0x0000
#define BUTTON_PIO_HAS_TRI 0
#define BUTTON_PIO_HAS_OUT 0
#define BUTTON_PIO_HAS_IN 1
#define BUTTON_PIO_CAPTURE 1
#define BUTTON_PIO_EDGE_TYPE "ANY"
#define BUTTON_PIO_IRQ_TYPE "EDGE"
#define BUTTON_PIO_FREQ 48000000

/*
 * ext_flash configuration
 *
 */

#define EXT_FLASH_NAME "/dev/ext_flash"
#define EXT_FLASH_TYPE "altera_avalon_cfi_flash"
#define EXT_FLASH_BASE 0x00000000
#define EXT_FLASH_SETUP_VALUE 40
#define EXT_FLASH_WAIT_VALUE 160
#define EXT_FLASH_HOLD_VALUE 40
#define EXT_FLASH_TIMING_UNITS "ns"
#define EXT_FLASH_UNIT_MULTIPLIER 1
#define EXT_FLASH_SIZE 2097152

/*
 * dma configuration
 *
 */

#define DMA_NAME "/dev/dma"
#define DMA_TYPE "altera_avalon_dma"
#define DMA_BASE 0x00220040
#define DMA_IRQ 3
#define DMA_READADDRESS_RESET_VALUE 0x0
#define DMA_WRITEADDRESS_RESET_VALUE 0x0
#define DMA_LENGTH_RESET_VALUE 0x0
#define DMA_CONTROL_BYTE_RESET_VALUE 0
#define DMA_CONTROL_HW_RESET_VALUE 0
#define DMA_CONTROL_WORD_RESET_VALUE 1
#define DMA_CONTROL_GO_RESET_VALUE 0
#define DMA_CONTROL_I_EN_RESET_VALUE 0
#define DMA_CONTROL_REEN_RESET_VALUE 0
#define DMA_CONTROL_WEEN_RESET_VALUE 0
#define DMA_CONTROL_LEEN_RESET_VALUE 1
#define DMA_CONTROL_RCON_RESET_VALUE 0
#define DMA_CONTROL_WCON_RESET_VALUE 0
#define DMA_CONTROL_DOUBLEWORD_RESET_VALUE 0
#define DMA_CONTROL_QUADWORD_RESET_VALUE 0
#define DMA_CONTROL_SOFTWARERESET_RESET_VALUE 0
#define DMA_LENGTHWIDTH 13
#define DMA_BURST_ENABLE 0
#define DMA_FIFO_IN_LOGIC_ELEMENTS 1
#define DMA_ALLOW_BYTE_TRANSACTIONS 1
#define DMA_ALLOW_HW_TRANSACTIONS 1
#define DMA_ALLOW_WORD_TRANSACTIONS 1
#define DMA_ALLOW_DOUBLEWORD_TRANSACTIONS 1
#define DMA_ALLOW_QUADWORD_TRANSACTIONS 1
#define DMA_MAX_BURST_SIZE 128

/*
 * sysid configuration
 *
 */

#define SYSID_NAME "/dev/sysid"
#define SYSID_TYPE "altera_avalon_sysid"
#define SYSID_BASE 0x00220068
#define SYSID_ID 2658071710u
#define SYSID_TIMESTAMP 1148037945u

/*
 * sdram configuration
 *
 */

#define SDRAM_NAME "/dev/sdram"
#define SDRAM_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_BASE 0x00800000
#define SDRAM_REGISTER_DATA_IN 1
#define SDRAM_SIM_MODEL_BASE 0
#define SDRAM_SDRAM_DATA_WIDTH 16
#define SDRAM_SDRAM_ADDR_WIDTH 12
#define SDRAM_SDRAM_ROW_WIDTH 12
#define SDRAM_SDRAM_COL_WIDTH 8
#define SDRAM_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_SDRAM_NUM_BANKS 4
#define SDRAM_REFRESH_PERIOD 15.625
#define SDRAM_POWERUP_DELAY 200
#define SDRAM_CAS_LATENCY 3
#define SDRAM_T_RFC 65
#define SDRAM_T_RP 20
#define SDRAM_T_MRD 3
#define SDRAM_T_RCD 20
#define SDRAM_T_AC 5.4
#define SDRAM_T_WR 14
#define SDRAM_INIT_REFRESH_COMMANDS 2
#define SDRAM_INIT_NOP_DELAY 0
#define SDRAM_SHARED_DATA 1
#define SDRAM_STARVATION_INDICATOR 0
#define SDRAM_TRISTATE_BRIDGE_SLAVE "ext_mem_bus/avalon_slave"
#define SDRAM_IS_INITIALIZED 1
#define SDRAM_SDRAM_BANK_WIDTH 2

/*
 * sram configuration
 *
 */

#define SRAM_NAME "/dev/sram"
#define SRAM_TYPE "Sram_UP3"
#define SRAM_BASE 0x00200000
#define SRAM_SRAM_MEMORY_SIZE 128
#define SRAM_SRAM_MEMORY_UNITS 1024
#define SRAM_SRAM_DATA_WIDTH 16

/*
 * ext_mem_bus configuration
 *
 */

#define EXT_MEM_BUS_NAME "/dev/ext_mem_bus"
#define EXT_MEM_BUS_TYPE "altera_avalon_tri_state_bridge"

/*
 * vga configuration
 *
 */

#define VGA_NAME "/dev/vga"
#define VGA_TYPE "vga"
#define VGA_BASE 0x01000000

/*
 * lcd configuration
 *
 */

#define LCD_NAME "/dev/lcd"
#define LCD_TYPE "sls_tristate_16x2_character_lcd"
#define LCD_BASE 0x00220000

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK TIMER1
#define ALT_TIMESTAMP_CLK none

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       SDRAM
#define ALT_RODATA_DEVICE     SDRAM
#define ALT_RWDATA_DEVICE     SDRAM
#define ALT_EXCEPTIONS_DEVICE SDRAM
#define ALT_RESET_DEVICE      EXT_FLASH


#endif /* __SYSTEM_H_ */