fpga_pre.v

用FPGA实现任意波形发生器的源代码

`include "rec.v"
`include "sec.v"

module fpga_pre(clk,rst,s_start,rec,sec,para0);
input clk,rst,rec,s_start;

//send
output sec;		
reg    sec;

//clk
reg bclk;
reg [7:0] cnt;

//mcu to fpga
output [7:0] para0;
reg   [7:0]  para0;
reg   [7:0]  addr_w,data_in,control,addRam;

reg [7:0] para_addr,para_data;
reg temp;

reg [19:0] phaseCom,phase_add;
reg clk_ram;

//fpga to mcu
reg   [7:0] result;		//out--temp
reg   [7:0] para  ;		//in--temp
//reg--state
reg   [3:0] para_s;		//in--state
reg   [3:0] result_s;	//out--state

//state
reg   r_done	  ;		//receive--done
reg   s_done	  ;		//send--done

reg clk_ram	;

//inst
rec inst0(bclk,rst,rec,r_done,para);
sec inst1(bclk,rst,s_start,result,sec,s_done);

//make--bclk
always@ ( posedge clk )
	begin
		if(cnt==64)
			begin
				cnt=0;
				bclk=~bclk;
			end
		else 
			cnt=cnt+1;
					
					
	
	clk_ram=~clk_ram;				
		
			
	end	

//receive para
always @ (  posedge r_done)
	begin
	 	if(!rst)	begin para_s=0;temp=0;end
	 	else
		begin	
		case(para_s)
		0:	if(para==8'h55) begin para_s=1;temp=0;end
		1:	begin para_addr=para;para_s=2;end
		2:	begin para_data=para;para_s=0;temp=1;end
		default:para_s=0	;
		endcase
		end
	end


always @ ( posedge temp )
	begin
		if(!rst)	begin addr_w=0;data_in=0;phaseCom=0;control=0;end
		else
		case(para_addr)
		1:addr_w=para;	//wr--address
		2:data_in=para;	//data
		3:phaseCom[19:16]=para;   //k[19:6]
		4:phaseCom[15:8]=para;   //k[15:8]
		5:phaseCom[7:0]=para;	//k[7:0]
		6:control=para;	//control
		default:    ;
		endcase
	end
//main
always@(posedge clk_ram )			
 	begin 	
	if(!rst)  begin phase_add=0; addRam=0;end
		else
		
		 if(  control[1] )	 //0---write 1---read
			begin 
					phase_add=phase_add+phaseCom;
					addRam=phase_add[19:14];
					
			end	
			else   
				addRam=addr_w ; 
	    
	end

//assign addRam = control[1] ==1?addr_r:addr_w;

//ram
lpm_ram_dq inst_ram( .data(data_in), .address(addRam),.we( control[0]), .q(para0) ) ;
				defparam inst_ram.lpm_width=8;
				defparam inst_ram.lpm_widthad=6;
				defparam inst_ram.lpm_indata="UNREGISTERED";
				defparam inst_ram.lpm_address_control="UNREGISTERED";
				defparam inst_ram.lpm_outdata="UNREGISTERED";
		



/*
	
//send--result
always @ (  posedge s_done)
	begin
			if( !rst ) begin result_s=0;end
			else
			begin
			case(result_s)
			0:result=8'hFF;		//zhentou
			1:result=8'hFE;		//zhentou
		//	2:result=para0;		
		//	3:result=para1;
		//	4:result=para2;
			5:result=8'hfD;		//zhenwei
			default:result_s=0	  ;
			endcase
			result_s=result_s+1;
			if(result_s==6)result_s=0;
			end
	end			
*/	
endmodule