📄 seg.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity seg is
port(a:in std_logic_vector(3 downto 1);
clk:in std_logic;
q:out std_logic_vector(6 downto 0));
end seg;
architecture seg_arc of seg is
begin
process(clk)
begin
if(clk'event and clk='1')then
case a is
when"001"=>q<="0000110";
when"010"=>q<="1011011";
when"100"=>q<="1001111";
when others=>null;
end case;
end if;
end process;
end seg_arc;
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