driver.vm

汽车四轮定位CCD驱动CPLD源代码

//
// Written by Synplify
// Sun Apr 20 15:12:14 2003
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\d:\isptools\synpbase\lib\vhd\std.vhd "
// file 2 "\e:\tcd-1208\2003.4.20\driver.vhd "
// file 3 "\d:\isptools\synpbase\lib\vhd\std1164.vhd "
// file 4 "\d:\isptools\synpbase\lib\vhd\arith.vhd "

`timescale 100 ps/100 ps
module MACH_DFF (
  Q,
  D,
  CLK,
  R,
  S,
  NOTIFIER
);
output Q;
input D;
input CLK;
input R;
input S;
input NOTIFIER;
wire Q ;
wire D ;
wire CLK ;
wire R ;
wire S ;
wire NOTIFIER ;
wire un0 ;
wire un1 ;
wire true ;
wire false ;
  assign #(1)  un0 = ~ S;
  assign #(1)  un1 = ~ R;
  assign true = 1'b1;
  assign false = 1'b0;
  reg r_e_g0; // dffrs
  always @(posedge CLK or posedge un1 or posedge un0 )
    r_e_g0 = #1 un1 ? 1'b0 : (un0 ? 1'b1 : D );
  assign Q = r_e_g0;
endmodule /* MACH_DFF */

module DFF (
  Q,
  D,
  CLK
);
output Q;
input D;
input CLK;
wire Q ;
wire D ;
wire CLK ;
wire un0 ;
wire true ;
wire notifier ;
wire false ;
  MACH_DFF INS4 (
	.Q(un0),
	.D(D),
	.CLK(CLK),
	.R(true),
	.S(true),
	.NOTIFIER(notifier)
);
  assign true = 1'b1;
  assign false = 1'b0;
  assign notifier = 1'b0;
assign Q = un0;
endmodule /* DFF */

module DFFRH (
  Q,
  D,
  CLK,
  R
);
output Q;
input D;
input CLK;
input R;
wire Q ;
wire D ;
wire CLK ;
wire R ;
wire un0 ;
wire un1 ;
wire true ;
wire notifier ;
wire false ;
  MACH_DFF INS1 (
	.Q(un0),
	.D(D),
	.CLK(CLK),
	.R(un1),
	.S(true),
	.NOTIFIER(notifier)
);
  assign #(1)  un1 = ~ R;
  assign true = 1'b1;
  assign false = 1'b0;
  assign notifier = 1'b0;
assign Q = un0;
endmodule /* DFFRH */

module OBUF (
  O,
  I0
);
output O;
input I0;
wire O ;
wire I0 ;
wire true ;
wire false ;
  assign #(1)  O = I0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* OBUF */

module DFFSH (
  Q,
  D,
  CLK,
  S
);
output Q;
input D;
input CLK;
input S;
wire Q ;
wire D ;
wire CLK ;
wire S ;
wire un0 ;
wire true ;
wire un1 ;
wire notifier ;
wire false ;
  MACH_DFF INS5 (
	.Q(un0),
	.D(D),
	.CLK(CLK),
	.R(true),
	.S(un1),
	.NOTIFIER(notifier)
);
  assign #(1)  un1 = ~ S;
  assign true = 1'b1;
  assign false = 1'b0;
  assign notifier = 1'b0;
assign Q = un0;
endmodule /* DFFSH */

module IBUF (
  O,
  I0
);
output O;
input I0;
wire O ;
wire I0 ;
wire true ;
wire false ;
  assign #(1)  O = I0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* IBUF */

module AND2 (
  O,
  I0,
  I1
);
output O;
input I0;
input I1;
wire O ;
wire I0 ;
wire I1 ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  O = I0  & I1 ;
endmodule /* AND2 */

module INV (
  O,
  I0
);
output O;
input I0;
wire O ;
wire I0 ;
wire true ;
wire false ;
  assign #(1)  O = ~ I0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* INV */

module OR2 (
  O,
  I0,
  I1
);
output O;
input I0;
input I1;
wire O ;
wire I0 ;
wire I1 ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  O = I0  | I1 ;
endmodule /* OR2 */

module XOR2 (
  O,
  I0,
  I1
);
output O;
input I0;
input I1;
wire O ;
wire I0 ;
wire I1 ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  O = I0  ^ I1 ;
endmodule /* XOR2 */

module Driver (
  Efficiant,
  Latch,
  SH,
  data1,
  data2,
  clk,
  reset,
  ccdin,
  askdata,
  dataclk,
  addr0,
  addr1,
  addr2,
  addr3
);
output Efficiant;
output Latch;
output SH;
output data1;
output data2;
input clk;
input reset;
input ccdin;
input askdata;
input dataclk;
input addr0;
input addr1;
input addr2;
input addr3;
wire Efficiant ;
wire Latch ;
wire SH ;
wire data1 ;
wire data2 ;
wire clk ;
wire reset ;
wire ccdin ;
wire askdata ;
wire dataclk ;
wire addr0 ;
wire addr1 ;
wire addr2 ;
wire addr3 ;
wire [11:0] countc;
wire [11:0] jumpdown;
wire [31:21] un6_countc;
wire [11:0] jumpup;
wire [11:0] countc_i_0;
wire tempefficiant_4 ;
wire data1_14 ;
wire data2_14 ;
wire N_1 ;
wire N_2 ;
wire N_3 ;
wire N_4 ;
wire N_5 ;
wire N_6 ;
wire N_7 ;
wire N_8 ;
wire N_9 ;
wire N_10 ;
wire N_13 ;
wire N_14 ;
wire N_15 ;
wire N_16 ;
wire N_17 ;
wire N_18 ;
wire N_19 ;
wire N_20 ;
wire N_21 ;
wire N_22 ;
wire N_31 ;
wire N_34 ;
wire N_37 ;
wire N_40 ;
wire N_43 ;
wire N_46 ;
wire N_49 ;
wire N_52 ;
wire N_55 ;
wire N_58 ;
wire N_108 ;
wire N_111 ;
wire N_112 ;
wire N_113 ;
wire N_114 ;
wire N_115 ;
wire N_116 ;
wire N_117 ;
wire N_118 ;
wire N_119 ;
wire N_120 ;
wire N_121 ;
wire N_122 ;
wire N_123 ;
wire N_124 ;
wire N_126 ;
wire N_127 ;
wire N_129 ;
wire N_130 ;
wire N_131 ;
wire N_132 ;
wire N_133 ;
wire templatch_4 ;
wire N_166 ;
wire N_167 ;
wire addr2_i ;
wire SH_i_0 ;
wire clk_i_0 ;
wire ccdin_i_0 ;
wire Efficiant_c ;
wire Latch_c ;
wire SH_c ;
wire data1_c ;
wire data2_c ;
wire clk_c ;
wire reset_c ;
wire ccdin_c ;
wire askdata_c ;
wire dataclk_c ;
wire addr0_c ;
wire addr1_c ;
wire addr2_c ;
wire addr3_c ;
wire N_168 ;
wire N_169 ;
wire N_133_i ;
wire N_131_i ;
wire N_132_i ;
wire N_182 ;
wire N_129_i ;
wire N_130_i ;
wire N_110_i_0 ;
wire N_108_i_0 ;
wire N_105_i_0 ;
wire N_107_i_0 ;
wire N_89_i ;
wire N_96_i ;
wire N_94_i ;
wire N_92_i ;
wire N_98_i ;
wire N_106_i ;
wire N_104_i ;
wire N_194 ;
wire N_195 ;
wire N_196 ;
wire N_197 ;
wire N_198 ;
wire N_199 ;
wire N_200 ;
wire N_201 ;
wire N_202 ;
wire N_203 ;
wire \templatch_4_f0_0_mux2.un3  ;
wire \templatch_4_f0_0_mux2.un1  ;
wire \templatch_4_f0_0_mux2.un0  ;
wire \G_100.un3  ;
wire \G_100.un1  ;
wire \G_100.un0  ;
wire \G_101.un3  ;
wire \G_101.un1  ;
wire \G_101.un0  ;
wire \G_102.un3  ;
wire \G_102.un1  ;
wire \G_102.un0  ;
wire \G_103.un3  ;
wire \G_103.un1  ;
wire \G_103.un0  ;
wire \G_104.un3  ;
wire \G_104.un1  ;
wire \G_104.un0  ;
wire \G_105.un3  ;
wire \G_105.un1  ;
wire \G_105.un0  ;
wire \G_106.un3  ;
wire \G_106.un1  ;
wire \G_106.un0  ;
wire \G_107.un3  ;
wire \G_107.un1  ;
wire \G_107.un0  ;
wire \G_108.un3  ;
wire \G_108.un1  ;
wire \G_108.un0  ;
wire \G_109.un3  ;
wire \G_109.un1  ;
wire \G_109.un0  ;
wire \G_110.un3  ;
wire \G_110.un1  ;
wire \G_110.un0  ;
wire \G_111.un3  ;
wire \G_111.un1  ;
wire \G_111.un0  ;
wire \G_112.un3  ;
wire \G_112.un1  ;
wire \G_112.un0  ;
wire \G_113.un3  ;
wire \G_113.un1  ;
wire \G_113.un0  ;
wire \data1_14_10_0.un3  ;
wire \data1_14_10_0.un1  ;
wire \data1_14_10_0.un0  ;
wire \data1_14_12_0.un3  ;
wire \data1_14_12_0.un1  ;
wire \data1_14_12_0.un0  ;
wire \data2_14_1_0.un3  ;
wire \data2_14_1_0.un1  ;
wire \data2_14_1_0.un0  ;
wire \data2_14_2_0.un3  ;
wire \data2_14_2_0.un1  ;
wire \data2_14_2_0.un0  ;
wire \data2_14_3_0.un3  ;
wire \data2_14_3_0.un1  ;
wire \data2_14_3_0.un0  ;
wire \data2_14_4_0.un3  ;
wire \data2_14_4_0.un1  ;
wire \data2_14_4_0.un0  ;
wire \data2_14_5_0.un3  ;
wire \data2_14_5_0.un1  ;
wire \data2_14_5_0.un0  ;
wire \data2_14_6_0.un3  ;
wire \data2_14_6_0.un1  ;
wire \data2_14_6_0.un0  ;
wire \data2_14_7_0.un3  ;
wire \data2_14_7_0.un1  ;
wire \data2_14_7_0.un0  ;
wire \data2_14_8_0.un3  ;
wire \data2_14_8_0.un1  ;
wire \data2_14_8_0.un0  ;
wire \data2_14_9_0.un3  ;
wire \data2_14_9_0.un1  ;
wire \data2_14_9_0.un0  ;
wire \data2_14_10_0.un3  ;
wire \data2_14_10_0.un1  ;
wire \data2_14_10_0.un0  ;
wire \data2_14_12_0.un3  ;
wire \data2_14_12_0.un1  ;
wire \data2_14_12_0.un0  ;
wire \data1_14_1_0.un3  ;
wire \data1_14_1_0.un1  ;
wire \data1_14_1_0.un0  ;
wire \data1_14_2_0.un3  ;
wire \data1_14_2_0.un1  ;
wire \data1_14_2_0.un0  ;
wire \data1_14_3_0.un3  ;
wire \data1_14_3_0.un1  ;
wire \data1_14_3_0.un0  ;
wire \data1_14_4_0.un3  ;
wire \data1_14_4_0.un1  ;
wire \data1_14_4_0.un0  ;
wire \data1_14_5_0.un3  ;
wire \data1_14_5_0.un1  ;
wire \data1_14_5_0.un0  ;
wire \data1_14_6_0.un3  ;
wire \data1_14_6_0.un1  ;
wire \data1_14_6_0.un0  ;
wire \data1_14_7_0.un3  ;
wire \data1_14_7_0.un1  ;
wire \data1_14_7_0.un0  ;
wire \data1_14_8_0.un3  ;
wire \data1_14_8_0.un1  ;
wire \data1_14_8_0.un0  ;
wire \data1_14_9_0.un3  ;
wire \data1_14_9_0.un1  ;
wire \data1_14_9_0.un0  ;
wire GND ;
wire VCC ;
// @2:75
  DFF \jumpdown_Z[2]  (
	.Q(jumpdown[2]),
	.D(N_113),
	.CLK(ccdin_i_0)
);
// @2:75
  DFF \jumpdown_Z[3]  (
	.Q(jumpdown[3]),
	.D(N_114),
	.CLK(ccdin_i_0)
);
// @2:75
  DFF \jumpdown_Z[4]  (
	.Q(jumpdown[4]),
	.D(N_115),
	.CLK(ccdin_i_0)
);
// @2:75
  DFF \jumpdown_Z[5]  (
	.Q(jumpdown[5]),
	.D(N_116),
	.CLK(ccdin_i_0)
);
// @2:75
  DFF \jumpdown_Z[6]  (
	.Q(jumpdown[6]),
	.D(N_117),
	.CLK(ccdin_i_0)
);
// @2:75
  DFF \jumpdown_Z[7]  (
	.Q(jumpdown[7]),
	.D(N_118),
	.CLK(ccdin_i_0)
);
// @2:75
  DFF \jumpdown_Z[8]  (
	.Q(jumpdown[8]),
	.D(N_119),
	.CLK(ccdin_i_0)
);
// @2:75
  DFF \jumpdown_Z[9]  (
	.Q(jumpdown[9]),
	.D(N_120),
	.CLK(ccdin_i_0)
);
// @2:75
  DFF \jumpdown_Z[10]  (
	.Q(jumpdown[10]),
	.D(N_121),
	.CLK(ccdin_i_0)
);
// @2:75
  DFF \jumpdown_Z[11]  (
	.Q(jumpdown[11]),
	.D(N_122),
	.CLK(ccdin_i_0)
);
// @2:39
  DFFRH \countc_Z[11]  (
	.Q(countc[11]),
	.D(N_98_i),
	.CLK(clk_i_0),
	.R(reset_c)
);
// @2:75
  DFF \jumpup_Z[0]  (
	.Q(jumpup[0]),
	.D(countc[0]),
	.CLK(ccdin_c)
);
// @2:75
  DFF \jumpup_Z[1]  (
	.Q(jumpup[1]),
	.D(countc[1]),
	.CLK(ccdin_c)
);
// @2:75
  DFF \jumpup_Z[2]  (
	.Q(jumpup[2]),
	.D(countc[2]),
	.CLK(ccdin_c)
);
// @2:75
  DFF \jumpup_Z[3]  (
	.Q(jumpup[3]),
	.D(countc[3]),
	.CLK(ccdin_c)
);
// @2:75
  DFF \jumpup_Z[4]  (
	.Q(jumpup[4]),
	.D(countc[4]),
	.CLK(ccdin_c)
);
// @2:75
  DFF \jumpup_Z[5]  (
	.Q(jumpup[5]),
	.D(countc[5]),
	.CLK(ccdin_c)
);
// @2:75
  DFF \jumpup_Z[6]  (
	.Q(jumpup[6]),
	.D(countc[6]),
	.CLK(ccdin_c)
);
// @2:75
  DFF \jumpup_Z[7]  (
	.Q(jumpup[7]),
	.D(countc[7]),
	.CLK(ccdin_c)
);
// @2:75
  DFF \jumpup_Z[8]  (
	.Q(jumpup[8]),
	.D(countc[8]),