counter2plus.vhm

来自「汽车四轮定位CCD驱动CPLD源代码」· VHM 代码 · 共 274 行

--
-- Written by Synplicity
-- Sat Apr 19 17:35:47 2003
--

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity MACH_DFF is
port(
  Q :  out std_logic;
  D :  in std_logic;
  CLK :  in std_logic;
  R :  in std_logic;
  S :  in std_logic;
  NOTIFIER :  in std_logic);
end MACH_DFF;

architecture beh of MACH_DFF is
  signal UN0 : std_logic ;
  signal UN1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  UN0 <= not S;
  UN1 <= not R;
  NN_1 <= '1';
  NN_2 <= '0';
  II_Q: prim_dff port map (Q, D, CLK, UN1, UN0);
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity AND2 is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  I1 :  in std_logic);
end AND2;

architecture beh of AND2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  O <= I0 and I1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity DFFRH is
port(
  Q :  out std_logic;
  D :  in std_logic;
  CLK :  in std_logic;
  R :  in std_logic);
end DFFRH;

architecture beh of DFFRH is
  signal UN1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NOTIFIER : std_logic ;
  signal NN_2 : std_logic ;
  component MACH_DFF
    port(Q :  out std_logic;
    D :  in std_logic;
    CLK :  in std_logic;
    R :  in std_logic;
    S :  in std_logic;
    NOTIFIER :  in std_logic  );
  end component;
begin
  II_INS1: MACH_DFF port map (
    Q => Q,
    D => D,
    CLK => CLK,
    R => UN1,
    S => NN_1,
    NOTIFIER => NOTIFIER);
  UN1 <= not R;
  NN_1 <= '1';
  NN_2 <= '0';
  NOTIFIER <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity IBUF is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end IBUF;

architecture beh of IBUF is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= I0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity INV is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end INV;

architecture beh of INV is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= not I0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity OBUF is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end OBUF;

architecture beh of OBUF is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= I0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity XOR2 is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  I1 :  in std_logic);
end XOR2;

architecture beh of XOR2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  O <= I0 xor I1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity counter2plus is
port(
  clk :  in std_logic;
  reset :  in std_logic;
  RS :  out std_logic;
  Gout :  out std_logic);
end counter2plus;

architecture beh of counter2plus is
  signal COUNTC : std_logic_vector(1 to 1);
  signal UN6_COUNTC : std_logic_vector(31 to 31);
  signal COUNTC_I : std_logic_vector(1 downto 0);
  signal COUNTC_C : std_logic_vector(0 to 0);
  signal TEMPRS_6 : std_logic ;
  signal CLK_C : std_logic ;
  signal RESET_C : std_logic ;
  signal RS_C : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  component DFFRH
    port(Q :  out std_logic;
    D :  in std_logic;
    CLK :  in std_logic;
    R :  in std_logic  );
  end component;
  component IBUF
    port(O :  out std_logic;
    I0 :  in std_logic  );
  end component;
  component OBUF
    port(O :  out std_logic;
    I0 :  in std_logic  );
  end component;
  component AND2
    port(O :  out std_logic;
    I0 :  in std_logic;
    I1 :  in std_logic  );
  end component;
  component XOR2
    port(O :  out std_logic;
    I0 :  in std_logic;
    I1 :  in std_logic  );
  end component;
  component INV
    port(O :  out std_logic;
    I0 :  in std_logic  );
  end component;
begin
  \II_COUNTC[0]\: DFFRH port map (
    Q => COUNTC_C(0),
    D => COUNTC_I(0),
    CLK => CLK_C,
    R => RESET_C);
  \II_COUNTC[1]\: DFFRH port map (
    Q => COUNTC(1),
    D => UN6_COUNTC(31),
    CLK => CLK_C,
    R => RESET_C);
  II_CLK: IBUF port map (
    O => CLK_C,
    I0 => clk);
  II_RESET: IBUF port map (
    O => RESET_C,
    I0 => reset);
  II_RSDFFRH: DFFRH port map (
    Q => RS_C,
    D => TEMPRS_6,
    CLK => CLK_C,
    R => RESET_C);
  II_RS: OBUF port map (
    O => RS,
    I0 => RS_C);
  II_GOUT: OBUF port map (
    O => Gout,
    I0 => COUNTC_C(0));
  II_TEMPRS_6: AND2 port map (
    O => TEMPRS_6,
    I0 => COUNTC_C(0),
    I1 => COUNTC_I(1));
  II_G_3: XOR2 port map (
    O => UN6_COUNTC(31),
    I0 => COUNTC(1),
    I1 => COUNTC_C(0));
  \II_COUNTC_I[0]\: INV port map (
    O => COUNTC_I(0),
    I0 => COUNTC_C(0));
  \II_COUNTC_I[1]\: INV port map (
    O => COUNTC_I(1),
    I0 => COUNTC(1));
  GND <= '0';
  VCC <= '1';
end beh;