part1.map.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 06 17:11:13 2007 " "Info: Processing started: Wed Jun 06 17:11:13 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part1 -c part1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part1 -c part1" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "two_and.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file two_and.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 two_and-one " "Info: Found design unit 1: two_and-one" {  } { { "two_and.vhd" "" { Text "E:/VHDL/实验4/part1/two_and.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 two_and " "Info: Found entity 1: two_and" {  } { { "two_and.vhd" "" { Text "E:/VHDL/实验4/part1/two_and.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"if\";  expecting \"end\", or \"(\", or an identifier (\"if\" is a reserved keyword), or a concurrent statement,  T_flip_flops.vhd(11) " "Error (10500): VHDL syntax error at T_flip_flops.vhd(11) near text \"if\";  expecting \"end\", or \"(\", or an identifier (\"if\" is a reserved keyword), or a concurrent statement, " {  } { { "T_flip_flops.vhd" "" { Text "E:/VHDL/实验4/part1/T_flip_flops.vhd" 11 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"elsif\";  expecting \"end\", or \"(\", or an identifier (\"elsif\" is a reserved keyword), or a concurrent statement,  T_flip_flops.vhd(12) " "Error (10500): VHDL syntax error at T_flip_flops.vhd(12) near text \"elsif\";  expecting \"end\", or \"(\", or an identifier (\"elsif\" is a reserved keyword), or a concurrent statement, " {  } { { "T_flip_flops.vhd" "" { Text "E:/VHDL/实验4/part1/T_flip_flops.vhd" 12 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"and\";  expecting \"(\", or \"'\", or \".\" T_flip_flops.vhd(12) " "Error (10500): VHDL syntax error at T_flip_flops.vhd(12) near text \"and\";  expecting \"(\", or \"'\", or \".\"" {  } { { "T_flip_flops.vhd" "" { Text "E:/VHDL/实验4/part1/T_flip_flops.vhd" 12 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"else\";  expecting \"end\", or \"(\", or an identifier (\"else\" is a reserved keyword), or a concurrent statement,  T_flip_flops.vhd(14) " "Error (10500): VHDL syntax error at T_flip_flops.vhd(14) near text \"else\";  expecting \"end\", or \"(\", or an identifier (\"else\" is a reserved keyword), or a concurrent statement, " {  } { { "T_flip_flops.vhd" "" { Text "E:/VHDL/实验4/part1/T_flip_flops.vhd" 14 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"if\";  expecting \";\", or an identifier (\"if\" is a reserved keyword), or \"architecture\" T_flip_flops.vhd(15) " "Error (10500): VHDL syntax error at T_flip_flops.vhd(15) near text \"if\";  expecting \";\", or an identifier (\"if\" is a reserved keyword), or \"architecture\"" {  } { { "T_flip_flops.vhd" "" { Text "E:/VHDL/实验4/part1/T_flip_flops.vhd" 15 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "T_flip_flops.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file T_flip_flops.vhd" {  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 5 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 5 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Wed Jun 06 17:11:14 2007 " "Error: Processing ended: Wed Jun 06 17:11:14 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}