part2.fit.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.286 ns register register " "Info: Estimated most critical path is register to register delay of 2.286 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q1\[1\] 1 REG LAB_X1_Y10 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X1_Y10; Fanout = 3; REG Node = 'Q1\[1\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { Q1[1] } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.455 ns) + CELL(0.414 ns) 0.869 ns Q1\[1\]~77 2 COMB LAB_X1_Y10 2 " "Info: 2: + IC(0.455 ns) + CELL(0.414 ns) = 0.869 ns; Loc. = LAB_X1_Y10; Fanout = 2; COMB Node = 'Q1\[1\]~77'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.869 ns" { Q1[1] Q1[1]~77 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.940 ns Q1\[2\]~78 3 COMB LAB_X1_Y10 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.940 ns; Loc. = LAB_X1_Y10; Fanout = 2; COMB Node = 'Q1\[2\]~78'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[1]~77 Q1[2]~78 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.011 ns Q1\[3\]~79 4 COMB LAB_X1_Y10 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.011 ns; Loc. = LAB_X1_Y10; Fanout = 2; COMB Node = 'Q1\[3\]~79'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[2]~78 Q1[3]~79 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.082 ns Q1\[4\]~80 5 COMB LAB_X1_Y10 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.082 ns; Loc. = LAB_X1_Y10; Fanout = 2; COMB Node = 'Q1\[4\]~80'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[3]~79 Q1[4]~80 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.153 ns Q1\[5\]~81 6 COMB LAB_X1_Y10 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.153 ns; Loc. = LAB_X1_Y10; Fanout = 2; COMB Node = 'Q1\[5\]~81'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[4]~80 Q1[5]~81 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.224 ns Q1\[6\]~82 7 COMB LAB_X1_Y10 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.224 ns; Loc. = LAB_X1_Y10; Fanout = 2; COMB Node = 'Q1\[6\]~82'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[5]~81 Q1[6]~82 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.295 ns Q1\[7\]~83 8 COMB LAB_X1_Y10 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.295 ns; Loc. = LAB_X1_Y10; Fanout = 2; COMB Node = 'Q1\[7\]~83'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[6]~82 Q1[7]~83 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.366 ns Q1\[8\]~84 9 COMB LAB_X1_Y10 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 1.366 ns; Loc. = LAB_X1_Y10; Fanout = 2; COMB Node = 'Q1\[8\]~84'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[7]~83 Q1[8]~84 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.437 ns Q1\[9\]~85 10 COMB LAB_X1_Y10 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.437 ns; Loc. = LAB_X1_Y10; Fanout = 2; COMB Node = 'Q1\[9\]~85'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[8]~84 Q1[9]~85 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.508 ns Q1\[10\]~86 11 COMB LAB_X1_Y10 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 1.508 ns; Loc. = LAB_X1_Y10; Fanout = 2; COMB Node = 'Q1\[10\]~86'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[9]~85 Q1[10]~86 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.579 ns Q1\[11\]~87 12 COMB LAB_X1_Y10 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.579 ns; Loc. = LAB_X1_Y10; Fanout = 2; COMB Node = 'Q1\[11\]~87'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[10]~86 Q1[11]~87 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.650 ns Q1\[12\]~88 13 COMB LAB_X1_Y10 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 1.650 ns; Loc. = LAB_X1_Y10; Fanout = 2; COMB Node = 'Q1\[12\]~88'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[11]~87 Q1[12]~88 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.721 ns Q1\[13\]~89 14 COMB LAB_X1_Y10 2 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 1.721 ns; Loc. = LAB_X1_Y10; Fanout = 2; COMB Node = 'Q1\[13\]~89'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[12]~88 Q1[13]~89 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.792 ns Q1\[14\]~90 15 COMB LAB_X1_Y10 1 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 1.792 ns; Loc. = LAB_X1_Y10; Fanout = 1; COMB Node = 'Q1\[14\]~90'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[13]~89 Q1[14]~90 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 2.202 ns Q1\[15\]~76 16 COMB LAB_X1_Y10 1 " "Info: 16: + IC(0.000 ns) + CELL(0.410 ns) = 2.202 ns; Loc. = LAB_X1_Y10; Fanout = 1; COMB Node = 'Q1\[15\]~76'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.410 ns" { Q1[14]~90 Q1[15]~76 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.286 ns Q1\[15\] 17 REG LAB_X1_Y10 2 " "Info: 17: + IC(0.000 ns) + CELL(0.084 ns) = 2.286 ns; Loc. = LAB_X1_Y10; Fanout = 2; REG Node = 'Q1\[15\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Q1[15]~76 Q1[15] } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.831 ns ( 80.10 % ) " "Info: Total cell delay = 1.831 ns ( 80.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.455 ns ( 19.90 % ) " "Info: Total interconnect delay = 0.455 ns ( 19.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.286 ns" { Q1[1] Q1[1]~77 Q1[2]~78 Q1[3]~79 Q1[4]~80 Q1[5]~81 Q1[6]~82 Q1[7]~83 Q1[8]~84 Q1[9]~85 Q1[10]~86 Q1[11]~87 Q1[12]~88 Q1[13]~89 Q1[14]~90 Q1[15]~76 Q1[15] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "16 " "Warning: Found 16 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[0\] 0 " "Info: Pin \"Q\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[1\] 0 " "Info: Pin \"Q\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[2\] 0 " "Info: Pin \"Q\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[3\] 0 " "Info: Pin \"Q\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[4\] 0 " "Info: Pin \"Q\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[5\] 0 " "Info: Pin \"Q\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[6\] 0 " "Info: Pin \"Q\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[7\] 0 " "Info: Pin \"Q\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[8\] 0 " "Info: Pin \"Q\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[9\] 0 " "Info: Pin \"Q\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[10\] 0 " "Info: Pin \"Q\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[11\] 0 " "Info: Pin \"Q\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[12\] 0 " "Info: Pin \"Q\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[13\] 0 " "Info: Pin \"Q\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[14\] 0 " "Info: Pin \"Q\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[15\] 0 " "Info: Pin \"Q\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 06 17:37:57 2007 " "Info: Processing ended: Wed Jun 06 17:37:57 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:20 " "Info: Elapsed time: 00:00:20" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/VHDL/实验4/part2/part2.fit.smsg " "Info: Generated suppressed messages file E:/VHDL/实验4/part2/part2.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}