part2.tan.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register Q1\[0\] register Q1\[15\] 385.06 MHz 2.597 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 385.06 MHz between source register \"Q1\[0\]\" and destination register \"Q1\[15\]\" (period= 2.597 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.383 ns + Longest register register " "Info: + Longest register to register delay is 2.383 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q1\[0\] 1 REG LCFF_X1_Y10_N31 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y10_N31; Fanout = 4; REG Node = 'Q1\[0\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { Q1[0] } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.464 ns) + CELL(0.414 ns) 0.878 ns Q1\[1\]~77 2 COMB LCCOMB_X1_Y10_N0 2 " "Info: 2: + IC(0.464 ns) + CELL(0.414 ns) = 0.878 ns; Loc. = LCCOMB_X1_Y10_N0; Fanout = 2; COMB Node = 'Q1\[1\]~77'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.878 ns" { Q1[0] Q1[1]~77 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.949 ns Q1\[2\]~78 3 COMB LCCOMB_X1_Y10_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.949 ns; Loc. = LCCOMB_X1_Y10_N2; Fanout = 2; COMB Node = 'Q1\[2\]~78'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[1]~77 Q1[2]~78 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.020 ns Q1\[3\]~79 4 COMB LCCOMB_X1_Y10_N4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.020 ns; Loc. = LCCOMB_X1_Y10_N4; Fanout = 2; COMB Node = 'Q1\[3\]~79'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[2]~78 Q1[3]~79 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.091 ns Q1\[4\]~80 5 COMB LCCOMB_X1_Y10_N6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.091 ns; Loc. = LCCOMB_X1_Y10_N6; Fanout = 2; COMB Node = 'Q1\[4\]~80'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[3]~79 Q1[4]~80 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.162 ns Q1\[5\]~81 6 COMB LCCOMB_X1_Y10_N8 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.162 ns; Loc. = LCCOMB_X1_Y10_N8; Fanout = 2; COMB Node = 'Q1\[5\]~81'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[4]~80 Q1[5]~81 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.233 ns Q1\[6\]~82 7 COMB LCCOMB_X1_Y10_N10 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.233 ns; Loc. = LCCOMB_X1_Y10_N10; Fanout = 2; COMB Node = 'Q1\[6\]~82'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[5]~81 Q1[6]~82 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.304 ns Q1\[7\]~83 8 COMB LCCOMB_X1_Y10_N12 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.304 ns; Loc. = LCCOMB_X1_Y10_N12; Fanout = 2; COMB Node = 'Q1\[7\]~83'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[6]~82 Q1[7]~83 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 1.463 ns Q1\[8\]~84 9 COMB LCCOMB_X1_Y10_N14 2 " "Info: 9: + IC(0.000 ns) + CELL(0.159 ns) = 1.463 ns; Loc. = LCCOMB_X1_Y10_N14; Fanout = 2; COMB Node = 'Q1\[8\]~84'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.159 ns" { Q1[7]~83 Q1[8]~84 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.534 ns Q1\[9\]~85 10 COMB LCCOMB_X1_Y10_N16 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.534 ns; Loc. = LCCOMB_X1_Y10_N16; Fanout = 2; COMB Node = 'Q1\[9\]~85'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[8]~84 Q1[9]~85 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.605 ns Q1\[10\]~86 11 COMB LCCOMB_X1_Y10_N18 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 1.605 ns; Loc. = LCCOMB_X1_Y10_N18; Fanout = 2; COMB Node = 'Q1\[10\]~86'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[9]~85 Q1[10]~86 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.676 ns Q1\[11\]~87 12 COMB LCCOMB_X1_Y10_N20 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.676 ns; Loc. = LCCOMB_X1_Y10_N20; Fanout = 2; COMB Node = 'Q1\[11\]~87'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[10]~86 Q1[11]~87 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.747 ns Q1\[12\]~88 13 COMB LCCOMB_X1_Y10_N22 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 1.747 ns; Loc. = LCCOMB_X1_Y10_N22; Fanout = 2; COMB Node = 'Q1\[12\]~88'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[11]~87 Q1[12]~88 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.818 ns Q1\[13\]~89 14 COMB LCCOMB_X1_Y10_N24 2 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 1.818 ns; Loc. = LCCOMB_X1_Y10_N24; Fanout = 2; COMB Node = 'Q1\[13\]~89'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[12]~88 Q1[13]~89 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.889 ns Q1\[14\]~90 15 COMB LCCOMB_X1_Y10_N26 1 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 1.889 ns; Loc. = LCCOMB_X1_Y10_N26; Fanout = 1; COMB Node = 'Q1\[14\]~90'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Q1[13]~89 Q1[14]~90 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 2.299 ns Q1\[15\]~76 16 COMB LCCOMB_X1_Y10_N28 1 " "Info: 16: + IC(0.000 ns) + CELL(0.410 ns) = 2.299 ns; Loc. = LCCOMB_X1_Y10_N28; Fanout = 1; COMB Node = 'Q1\[15\]~76'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.410 ns" { Q1[14]~90 Q1[15]~76 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.383 ns Q1\[15\] 17 REG LCFF_X1_Y10_N29 2 " "Info: 17: + IC(0.000 ns) + CELL(0.084 ns) = 2.383 ns; Loc. = LCFF_X1_Y10_N29; Fanout = 2; REG Node = 'Q1\[15\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Q1[15]~76 Q1[15] } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.919 ns ( 80.53 % ) " "Info: Total cell delay = 1.919 ns ( 80.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.464 ns ( 19.47 % ) " "Info: Total interconnect delay = 0.464 ns ( 19.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.383 ns" { Q1[0] Q1[1]~77 Q1[2]~78 Q1[3]~79 Q1[4]~80 Q1[5]~81 Q1[6]~82 Q1[7]~83 Q1[8]~84 Q1[9]~85 Q1[10]~86 Q1[11]~87 Q1[12]~88 Q1[13]~89 Q1[14]~90 Q1[15]~76 Q1[15] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.383 ns" { Q1[0] Q1[1]~77 Q1[2]~78 Q1[3]~79 Q1[4]~80 Q1[5]~81 Q1[6]~82 Q1[7]~83 Q1[8]~84 Q1[9]~85 Q1[10]~86 Q1[11]~87 Q1[12]~88 Q1[13]~89 Q1[14]~90 Q1[15]~76 Q1[15] } { 0.000ns 0.464ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.414ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.636 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.636 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLK'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLK~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'CLK~clkctrl'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.982 ns) + CELL(0.537 ns) 2.636 ns Q1\[15\] 3 REG LCFF_X1_Y10_N29 2 " "Info: 3: + IC(0.982 ns) + CELL(0.537 ns) = 2.636 ns; Loc. = LCFF_X1_Y10_N29; Fanout = 2; REG Node = 'Q1\[15\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.519 ns" { CLK~clkctrl Q1[15] } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 58.27 % ) " "Info: Total cell delay = 1.536 ns ( 58.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns ( 41.73 % ) " "Info: Total interconnect delay = 1.100 ns ( 41.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.636 ns" { CLK CLK~clkctrl Q1[15] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.636 ns" { CLK CLK~combout CLK~clkctrl Q1[15] } { 0.000ns 0.000ns 0.118ns 0.982ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.636 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.636 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLK'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLK~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'CLK~clkctrl'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.982 ns) + CELL(0.537 ns) 2.636 ns Q1\[0\] 3 REG LCFF_X1_Y10_N31 4 " "Info: 3: + IC(0.982 ns) + CELL(0.537 ns) = 2.636 ns; Loc. = LCFF_X1_Y10_N31; Fanout = 4; REG Node = 'Q1\[0\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.519 ns" { CLK~clkctrl Q1[0] } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 58.27 % ) " "Info: Total cell delay = 1.536 ns ( 58.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns ( 41.73 % ) " "Info: Total interconnect delay = 1.100 ns ( 41.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.636 ns" { CLK CLK~clkctrl Q1[0] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.636 ns" { CLK CLK~combout CLK~clkctrl Q1[0] } { 0.000ns 0.000ns 0.118ns 0.982ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.636 ns" { CLK CLK~clkctrl Q1[15] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.636 ns" { CLK CLK~combout CLK~clkctrl Q1[15] } { 0.000ns 0.000ns 0.118ns 0.982ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.636 ns" { CLK CLK~clkctrl Q1[0] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.636 ns" { CLK CLK~combout CLK~clkctrl Q1[0] } { 0.000ns 0.000ns 0.118ns 0.982ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.383 ns" { Q1[0] Q1[1]~77 Q1[2]~78 Q1[3]~79 Q1[4]~80 Q1[5]~81 Q1[6]~82 Q1[7]~83 Q1[8]~84 Q1[9]~85 Q1[10]~86 Q1[11]~87 Q1[12]~88 Q1[13]~89 Q1[14]~90 Q1[15]~76 Q1[15] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.383 ns" { Q1[0] Q1[1]~77 Q1[2]~78 Q1[3]~79 Q1[4]~80 Q1[5]~81 Q1[6]~82 Q1[7]~83 Q1[8]~84 Q1[9]~85 Q1[10]~86 Q1[11]~87 Q1[12]~88 Q1[13]~89 Q1[14]~90 Q1[15]~76 Q1[15] } { 0.000ns 0.464ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.414ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.636 ns" { CLK CLK~clkctrl Q1[15] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.636 ns" { CLK CLK~combout CLK~clkctrl Q1[15] } { 0.000ns 0.000ns 0.118ns 0.982ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.636 ns" { CLK CLK~clkctrl Q1[0] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.636 ns" { CLK CLK~combout CLK~clkctrl Q1[0] } { 0.000ns 0.000ns 0.118ns 0.982ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Q\[4\] Q1\[4\] 6.509 ns register " "Info: tco from clock \"CLK\" to destination pin \"Q\[4\]\" through register \"Q1\[4\]\" is 6.509 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.636 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.636 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLK'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLK~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'CLK~clkctrl'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.982 ns) + CELL(0.537 ns) 2.636 ns Q1\[4\] 3 REG LCFF_X1_Y10_N7 3 " "Info: 3: + IC(0.982 ns) + CELL(0.537 ns) = 2.636 ns; Loc. = LCFF_X1_Y10_N7; Fanout = 3; REG Node = 'Q1\[4\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.519 ns" { CLK~clkctrl Q1[4] } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 58.27 % ) " "Info: Total cell delay = 1.536 ns ( 58.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns ( 41.73 % ) " "Info: Total interconnect delay = 1.100 ns ( 41.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.636 ns" { CLK CLK~clkctrl Q1[4] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.636 ns" { CLK CLK~combout CLK~clkctrl Q1[4] } { 0.000ns 0.000ns 0.118ns 0.982ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.623 ns + Longest register pin " "Info: + Longest register to pin delay is 3.623 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q1\[4\] 1 REG LCFF_X1_Y10_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y10_N7; Fanout = 3; REG Node = 'Q1\[4\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { Q1[4] } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.981 ns) + CELL(2.642 ns) 3.623 ns Q\[4\] 2 PIN PIN_W3 0 " "Info: 2: + IC(0.981 ns) + CELL(2.642 ns) = 3.623 ns; Loc. = PIN_W3; Fanout = 0; PIN Node = 'Q\[4\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.623 ns" { Q1[4] Q[4] } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验4/part2/part2.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.642 ns ( 72.92 % ) " "Info: Total cell delay = 2.642 ns ( 72.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.981 ns ( 27.08 % ) " "Info: Total interconnect delay = 0.981 ns ( 27.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.623 ns" { Q1[4] Q[4] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "3.623 ns" { Q1[4] Q[4] } { 0.000ns 0.981ns } { 0.000ns 2.642ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.636 ns" { CLK CLK~clkctrl Q1[4] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.636 ns" { CLK CLK~combout CLK~clkctrl Q1[4] } { 0.000ns 0.000ns 0.118ns 0.982ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.623 ns" { Q1[4] Q[4] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "3.623 ns" { Q1[4] Q[4] } { 0.000ns 0.981ns } { 0.000ns 2.642ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 06 17:38:26 2007 " "Info: Processing ended: Wed Jun 06 17:38:26 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}