part5.map.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 05 08:53:14 2007 " "Info: Processing started: Tue Jun 05 08:53:14 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part5.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file part5.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 part5-bhv " "Info: Found design unit 1: part5-bhv" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验3/part5/part5.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 part5 " "Info: Found entity 1: part5" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验3/part5/part5.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fall_D_latch.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fall_D_latch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fall_D_latch-bhv " "Info: Found design unit 1: fall_D_latch-bhv" {  } { { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fall_D_latch " "Info: Found entity 1: fall_D_latch" {  } { { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "up_D_latch.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file up_D_latch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 up_D_latch-bhv " "Info: Found design unit 1: up_D_latch-bhv" {  } { { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 up_D_latch " "Info: Found entity 1: up_D_latch" {  } { { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seven_segment.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file seven_segment.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seven_segment-bhv " "Info: Found design unit 1: seven_segment-bhv" {  } { { "seven_segment.vhd" "" { Text "E:/VHDL/实验3/part5/seven_segment.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 seven_segment " "Info: Found entity 1: seven_segment" {  } { { "seven_segment.vhd" "" { Text "E:/VHDL/实验3/part5/seven_segment.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "part5 " "Info: Elaborating entity \"part5\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "up_D_latch up_D_latch:u1 " "Info: Elaborating entity \"up_D_latch\" for hierarchy \"up_D_latch:u1\"" {  } { { "part5.vhd" "u1" { Text "E:/VHDL/实验3/part5/part5.vhd" 38 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fall_D_latch fall_D_latch:u2 " "Info: Elaborating entity \"fall_D_latch\" for hierarchy \"fall_D_latch:u2\"" {  } { { "part5.vhd" "u2" { Text "E:/VHDL/实验3/part5/part5.vhd" 46 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_segment seven_segment:u3 " "Info: Elaborating entity \"seven_segment\" for hierarchy \"seven_segment:u3\"" {  } { { "part5.vhd" "u3" { Text "E:/VHDL/实验3/part5/part5.vhd" 54 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "178 " "Info: Implemented 178 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "18 " "Info: Implemented 18 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "56 " "Info: Implemented 56 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "104 " "Info: Implemented 104 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 05 08:53:16 2007 " "Info: Processing ended: Tue Jun 05 08:53:16 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}