part5.tan.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "ITDB_TSU_RESULT" "up_D_latch:u1\|Q\[9\] SW\[9\] KEY1 5.225 ns register " "Info: tsu for register \"up_D_latch:u1\|Q\[9\]\" (data pin = \"SW\[9\]\", clock pin = \"KEY1\") is 5.225 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.922 ns + Longest pin register " "Info: + Longest pin to register delay is 7.922 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns SW\[9\] 1 PIN PIN_AC6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_AC6; Fanout = 1; PIN Node = 'SW\[9\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { SW[9] } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验3/part5/part5.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.774 ns) + CELL(0.275 ns) 6.899 ns up_D_latch:u1\|Q\[9\]~37 2 COMB LCCOMB_X2_Y30_N30 2 " "Info: 2: + IC(5.774 ns) + CELL(0.275 ns) = 6.899 ns; Loc. = LCCOMB_X2_Y30_N30; Fanout = 2; COMB Node = 'up_D_latch:u1\|Q\[9\]~37'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "6.049 ns" { SW[9] up_D_latch:u1|Q[9]~37 } "NODE_NAME" } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.657 ns) + CELL(0.366 ns) 7.922 ns up_D_latch:u1\|Q\[9\] 3 REG LCFF_X1_Y30_N1 7 " "Info: 3: + IC(0.657 ns) + CELL(0.366 ns) = 7.922 ns; Loc. = LCFF_X1_Y30_N1; Fanout = 7; REG Node = 'up_D_latch:u1\|Q\[9\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.023 ns" { up_D_latch:u1|Q[9]~37 up_D_latch:u1|Q[9] } "NODE_NAME" } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.491 ns ( 18.82 % ) " "Info: Total cell delay = 1.491 ns ( 18.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.431 ns ( 81.18 % ) " "Info: Total interconnect delay = 6.431 ns ( 81.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "7.922 ns" { SW[9] up_D_latch:u1|Q[9]~37 up_D_latch:u1|Q[9] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "7.922 ns" { SW[9] SW[9]~combout up_D_latch:u1|Q[9]~37 up_D_latch:u1|Q[9] } { 0.000ns 0.000ns 5.774ns 0.657ns } { 0.000ns 0.850ns 0.275ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY1 destination 2.661 ns - Shortest register " "Info: - Shortest clock path from clock \"KEY1\" to destination register is 2.661 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns KEY1 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'KEY1'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { KEY1 } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验3/part5/part5.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns KEY1~clkctrl 2 COMB CLKCTRL_G3 32 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 32; COMB Node = 'KEY1~clkctrl'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.118 ns" { KEY1 KEY1~clkctrl } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验3/part5/part5.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.007 ns) + CELL(0.537 ns) 2.661 ns up_D_latch:u1\|Q\[9\] 3 REG LCFF_X1_Y30_N1 7 " "Info: 3: + IC(1.007 ns) + CELL(0.537 ns) = 2.661 ns; Loc. = LCFF_X1_Y30_N1; Fanout = 7; REG Node = 'up_D_latch:u1\|Q\[9\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.544 ns" { KEY1~clkctrl up_D_latch:u1|Q[9] } "NODE_NAME" } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.72 % ) " "Info: Total cell delay = 1.536 ns ( 57.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.125 ns ( 42.28 % ) " "Info: Total interconnect delay = 1.125 ns ( 42.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.661 ns" { KEY1 KEY1~clkctrl up_D_latch:u1|Q[9] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.661 ns" { KEY1 KEY1~combout KEY1~clkctrl up_D_latch:u1|Q[9] } { 0.000ns 0.000ns 0.118ns 1.007ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "7.922 ns" { SW[9] up_D_latch:u1|Q[9]~37 up_D_latch:u1|Q[9] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "7.922 ns" { SW[9] SW[9]~combout up_D_latch:u1|Q[9]~37 up_D_latch:u1|Q[9] } { 0.000ns 0.000ns 5.774ns 0.657ns } { 0.000ns 0.850ns 0.275ns 0.366ns } } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.661 ns" { KEY1 KEY1~clkctrl up_D_latch:u1|Q[9] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.661 ns" { KEY1 KEY1~combout KEY1~clkctrl up_D_latch:u1|Q[9] } { 0.000ns 0.000ns 0.118ns 1.007ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "KEY1 HEX4\[3\] fall_D_latch:u2\|Q\[14\] 9.887 ns register " "Info: tco from clock \"KEY1\" to destination pin \"HEX4\[3\]\" through register \"fall_D_latch:u2\|Q\[14\]\" is 9.887 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY1 source 2.697 ns + Longest register " "Info: + Longest clock path from clock \"KEY1\" to source register is 2.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns KEY1 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'KEY1'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { KEY1 } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验3/part5/part5.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns KEY1~clkctrl 2 COMB CLKCTRL_G3 32 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 32; COMB Node = 'KEY1~clkctrl'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.118 ns" { KEY1 KEY1~clkctrl } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验3/part5/part5.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.537 ns) 2.697 ns fall_D_latch:u2\|Q\[14\] 3 REG LCFF_X29_Y35_N1 7 " "Info: 3: + IC(1.043 ns) + CELL(0.537 ns) = 2.697 ns; Loc. = LCFF_X29_Y35_N1; Fanout = 7; REG Node = 'fall_D_latch:u2\|Q\[14\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.580 ns" { KEY1~clkctrl fall_D_latch:u2|Q[14] } "NODE_NAME" } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.95 % ) " "Info: Total cell delay = 1.536 ns ( 56.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.161 ns ( 43.05 % ) " "Info: Total interconnect delay = 1.161 ns ( 43.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.697 ns" { KEY1 KEY1~clkctrl fall_D_latch:u2|Q[14] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.697 ns" { KEY1 KEY1~combout KEY1~clkctrl fall_D_latch:u2|Q[14] } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.940 ns + Longest register pin " "Info: + Longest register to pin delay is 6.940 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fall_D_latch:u2\|Q\[14\] 1 REG LCFF_X29_Y35_N1 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y35_N1; Fanout = 7; REG Node = 'fall_D_latch:u2\|Q\[14\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { fall_D_latch:u2|Q[14] } "NODE_NAME" } } { "fall_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/fall_D_latch.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.805 ns) + CELL(0.150 ns) 0.955 ns seven_segment:u7\|Mux3~23 2 COMB LCCOMB_X27_Y35_N16 1 " "Info: 2: + IC(0.805 ns) + CELL(0.150 ns) = 0.955 ns; Loc. = LCCOMB_X27_Y35_N16; Fanout = 1; COMB Node = 'seven_segment:u7\|Mux3~23'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.955 ns" { fall_D_latch:u2|Q[14] seven_segment:u7|Mux3~23 } "NODE_NAME" } } { "seven_segment.vhd" "" { Text "E:/VHDL/实验3/part5/seven_segment.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.197 ns) + CELL(2.788 ns) 6.940 ns HEX4\[3\] 3 PIN PIN_V13 0 " "Info: 3: + IC(3.197 ns) + CELL(2.788 ns) = 6.940 ns; Loc. = PIN_V13; Fanout = 0; PIN Node = 'HEX4\[3\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.985 ns" { seven_segment:u7|Mux3~23 HEX4[3] } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验3/part5/part5.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.938 ns ( 42.33 % ) " "Info: Total cell delay = 2.938 ns ( 42.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.002 ns ( 57.67 % ) " "Info: Total interconnect delay = 4.002 ns ( 57.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "6.940 ns" { fall_D_latch:u2|Q[14] seven_segment:u7|Mux3~23 HEX4[3] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "6.940 ns" { fall_D_latch:u2|Q[14] seven_segment:u7|Mux3~23 HEX4[3] } { 0.000ns 0.805ns 3.197ns } { 0.000ns 0.150ns 2.788ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.697 ns" { KEY1 KEY1~clkctrl fall_D_latch:u2|Q[14] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.697 ns" { KEY1 KEY1~combout KEY1~clkctrl fall_D_latch:u2|Q[14] } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "6.940 ns" { fall_D_latch:u2|Q[14] seven_segment:u7|Mux3~23 HEX4[3] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "6.940 ns" { fall_D_latch:u2|Q[14] seven_segment:u7|Mux3~23 HEX4[3] } { 0.000ns 0.805ns 3.197ns } { 0.000ns 0.150ns 2.788ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "up_D_latch:u1\|Q\[13\] SW\[13\] KEY1 0.894 ns register " "Info: th for register \"up_D_latch:u1\|Q\[13\]\" (data pin = \"SW\[13\]\", clock pin = \"KEY1\") is 0.894 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY1 destination 2.697 ns + Longest register " "Info: + Longest clock path from clock \"KEY1\" to destination register is 2.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns KEY1 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'KEY1'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { KEY1 } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验3/part5/part5.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns KEY1~clkctrl 2 COMB CLKCTRL_G3 32 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 32; COMB Node = 'KEY1~clkctrl'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.118 ns" { KEY1 KEY1~clkctrl } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验3/part5/part5.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.537 ns) 2.697 ns up_D_latch:u1\|Q\[13\] 3 REG LCFF_X27_Y35_N15 7 " "Info: 3: + IC(1.043 ns) + CELL(0.537 ns) = 2.697 ns; Loc. = LCFF_X27_Y35_N15; Fanout = 7; REG Node = 'up_D_latch:u1\|Q\[13\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.580 ns" { KEY1~clkctrl up_D_latch:u1|Q[13] } "NODE_NAME" } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.95 % ) " "Info: Total cell delay = 1.536 ns ( 56.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.161 ns ( 43.05 % ) " "Info: Total interconnect delay = 1.161 ns ( 43.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.697 ns" { KEY1 KEY1~clkctrl up_D_latch:u1|Q[13] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.697 ns" { KEY1 KEY1~combout KEY1~clkctrl up_D_latch:u1|Q[13] } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.069 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.069 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns SW\[13\] 1 PIN PIN_D13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; PIN Node = 'SW\[13\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { SW[13] } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验3/part5/part5.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.150 ns) 1.985 ns up_D_latch:u1\|Q\[13\]~33 2 COMB LCCOMB_X27_Y35_N14 2 " "Info: 2: + IC(0.856 ns) + CELL(0.150 ns) = 1.985 ns; Loc. = LCCOMB_X27_Y35_N14; Fanout = 2; COMB Node = 'up_D_latch:u1\|Q\[13\]~33'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.006 ns" { SW[13] up_D_latch:u1|Q[13]~33 } "NODE_NAME" } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.069 ns up_D_latch:u1\|Q\[13\] 3 REG LCFF_X27_Y35_N15 7 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.069 ns; Loc. = LCFF_X27_Y35_N15; Fanout = 7; REG Node = 'up_D_latch:u1\|Q\[13\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.084 ns" { up_D_latch:u1|Q[13]~33 up_D_latch:u1|Q[13] } "NODE_NAME" } } { "up_D_latch.vhd" "" { Text "E:/VHDL/实验3/part5/up_D_latch.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.213 ns ( 58.63 % ) " "Info: Total cell delay = 1.213 ns ( 58.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.856 ns ( 41.37 % ) " "Info: Total interconnect delay = 0.856 ns ( 41.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.069 ns" { SW[13] up_D_latch:u1|Q[13]~33 up_D_latch:u1|Q[13] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.069 ns" { SW[13] SW[13]~combout up_D_latch:u1|Q[13]~33 up_D_latch:u1|Q[13] } { 0.000ns 0.000ns 0.856ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.697 ns" { KEY1 KEY1~clkctrl up_D_latch:u1|Q[13] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.697 ns" { KEY1 KEY1~combout KEY1~clkctrl up_D_latch:u1|Q[13] } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.069 ns" { SW[13] up_D_latch:u1|Q[13]~33 up_D_latch:u1|Q[13] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.069 ns" { SW[13] SW[13]~combout up_D_latch:u1|Q[13]~33 up_D_latch:u1|Q[13] } { 0.000ns 0.000ns 0.856ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 05 08:53:50 2007 " "Info: Processing ended: Tue Jun 05 08:53:50 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}