part5.hier_info

几个ＶＨＤＬ的编程实例

|part5
SW[0] => up_D_latch:u1.D[0]
SW[0] => fall_D_latch:u2.D[0]
SW[1] => up_D_latch:u1.D[1]
SW[1] => fall_D_latch:u2.D[1]
SW[2] => up_D_latch:u1.D[2]
SW[2] => fall_D_latch:u2.D[2]
SW[3] => up_D_latch:u1.D[3]
SW[3] => fall_D_latch:u2.D[3]
SW[4] => up_D_latch:u1.D[4]
SW[4] => fall_D_latch:u2.D[4]
SW[5] => up_D_latch:u1.D[5]
SW[5] => fall_D_latch:u2.D[5]
SW[6] => up_D_latch:u1.D[6]
SW[6] => fall_D_latch:u2.D[6]
SW[7] => up_D_latch:u1.D[7]
SW[7] => fall_D_latch:u2.D[7]
SW[8] => up_D_latch:u1.D[8]
SW[8] => fall_D_latch:u2.D[8]
SW[9] => up_D_latch:u1.D[9]
SW[9] => fall_D_latch:u2.D[9]
SW[10] => up_D_latch:u1.D[10]
SW[10] => fall_D_latch:u2.D[10]
SW[11] => up_D_latch:u1.D[11]
SW[11] => fall_D_latch:u2.D[11]
SW[12] => up_D_latch:u1.D[12]
SW[12] => fall_D_latch:u2.D[12]
SW[13] => up_D_latch:u1.D[13]
SW[13] => fall_D_latch:u2.D[13]
SW[14] => up_D_latch:u1.D[14]
SW[14] => fall_D_latch:u2.D[14]
SW[15] => up_D_latch:u1.D[15]
SW[15] => fall_D_latch:u2.D[15]
KEY0 => up_D_latch:u1.RST
KEY0 => fall_D_latch:u2.RST
KEY1 => up_D_latch:u1.CLK
KEY1 => fall_D_latch:u2.CLK
HEX0[0] <= seven_segment:u3.show[0]
HEX0[1] <= seven_segment:u3.show[1]
HEX0[2] <= seven_segment:u3.show[2]
HEX0[3] <= seven_segment:u3.show[3]
HEX0[4] <= seven_segment:u3.show[4]
HEX0[5] <= seven_segment:u3.show[5]
HEX0[6] <= seven_segment:u3.show[6]
HEX1[0] <= seven_segment:u4.show[0]
HEX1[1] <= seven_segment:u4.show[1]
HEX1[2] <= seven_segment:u4.show[2]
HEX1[3] <= seven_segment:u4.show[3]
HEX1[4] <= seven_segment:u4.show[4]
HEX1[5] <= seven_segment:u4.show[5]
HEX1[6] <= seven_segment:u4.show[6]
HEX2[0] <= seven_segment:u5.show[0]
HEX2[1] <= seven_segment:u5.show[1]
HEX2[2] <= seven_segment:u5.show[2]
HEX2[3] <= seven_segment:u5.show[3]
HEX2[4] <= seven_segment:u5.show[4]
HEX2[5] <= seven_segment:u5.show[5]
HEX2[6] <= seven_segment:u5.show[6]
HEX3[0] <= seven_segment:u6.show[0]
HEX3[1] <= seven_segment:u6.show[1]
HEX3[2] <= seven_segment:u6.show[2]
HEX3[3] <= seven_segment:u6.show[3]
HEX3[4] <= seven_segment:u6.show[4]
HEX3[5] <= seven_segment:u6.show[5]
HEX3[6] <= seven_segment:u6.show[6]
HEX4[0] <= seven_segment:u7.show[0]
HEX4[1] <= seven_segment:u7.show[1]
HEX4[2] <= seven_segment:u7.show[2]
HEX4[3] <= seven_segment:u7.show[3]
HEX4[4] <= seven_segment:u7.show[4]
HEX4[5] <= seven_segment:u7.show[5]
HEX4[6] <= seven_segment:u7.show[6]
HEX5[0] <= seven_segment:u8.show[0]
HEX5[1] <= seven_segment:u8.show[1]
HEX5[2] <= seven_segment:u8.show[2]
HEX5[3] <= seven_segment:u8.show[3]
HEX5[4] <= seven_segment:u8.show[4]
HEX5[5] <= seven_segment:u8.show[5]
HEX5[6] <= seven_segment:u8.show[6]
HEX6[0] <= seven_segment:u9.show[0]
HEX6[1] <= seven_segment:u9.show[1]
HEX6[2] <= seven_segment:u9.show[2]
HEX6[3] <= seven_segment:u9.show[3]
HEX6[4] <= seven_segment:u9.show[4]
HEX6[5] <= seven_segment:u9.show[5]
HEX6[6] <= seven_segment:u9.show[6]
HEX7[0] <= seven_segment:u10.show[0]
HEX7[1] <= seven_segment:u10.show[1]
HEX7[2] <= seven_segment:u10.show[2]
HEX7[3] <= seven_segment:u10.show[3]
HEX7[4] <= seven_segment:u10.show[4]
HEX7[5] <= seven_segment:u10.show[5]
HEX7[6] <= seven_segment:u10.show[6]


|part5|up_D_latch:u1
CLK => Q[0]~reg0.CLK
CLK => Q[1]~reg0.CLK
CLK => Q[2]~reg0.CLK
CLK => Q[3]~reg0.CLK
CLK => Q[4]~reg0.CLK
CLK => Q[5]~reg0.CLK
CLK => Q[6]~reg0.CLK
CLK => Q[7]~reg0.CLK
CLK => Q[8]~reg0.CLK
CLK => Q[9]~reg0.CLK
CLK => Q[10]~reg0.CLK
CLK => Q[11]~reg0.CLK
CLK => Q[12]~reg0.CLK
CLK => Q[13]~reg0.CLK
CLK => Q[14]~reg0.CLK
CLK => Q[15]~reg0.CLK
RST => Q[0]~reg0.PRESET
RST => Q[1]~reg0.PRESET
RST => Q[2]~reg0.PRESET
RST => Q[3]~reg0.PRESET
RST => Q[4]~reg0.PRESET
RST => Q[5]~reg0.PRESET
RST => Q[6]~reg0.PRESET
RST => Q[7]~reg0.PRESET
RST => Q[8]~reg0.PRESET
RST => Q[9]~reg0.PRESET
RST => Q[10]~reg0.PRESET
RST => Q[11]~reg0.PRESET
RST => Q[12]~reg0.PRESET
RST => Q[13]~reg0.PRESET
RST => Q[14]~reg0.PRESET
RST => Q[15]~reg0.PRESET
D[0] => Q[0]~reg0.DATAIN
D[1] => Q[1]~reg0.DATAIN
D[2] => Q[2]~reg0.DATAIN
D[3] => Q[3]~reg0.DATAIN
D[4] => Q[4]~reg0.DATAIN
D[5] => Q[5]~reg0.DATAIN
D[6] => Q[6]~reg0.DATAIN
D[7] => Q[7]~reg0.DATAIN
D[8] => Q[8]~reg0.DATAIN
D[9] => Q[9]~reg0.DATAIN
D[10] => Q[10]~reg0.DATAIN
D[11] => Q[11]~reg0.DATAIN
D[12] => Q[12]~reg0.DATAIN
D[13] => Q[13]~reg0.DATAIN
D[14] => Q[14]~reg0.DATAIN
D[15] => Q[15]~reg0.DATAIN
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[10] <= Q[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[11] <= Q[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[12] <= Q[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[13] <= Q[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[14] <= Q[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[15] <= Q[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|part5|fall_D_latch:u2
CLK => Q[0]~reg0.CLK
CLK => Q[1]~reg0.CLK
CLK => Q[2]~reg0.CLK
CLK => Q[3]~reg0.CLK
CLK => Q[4]~reg0.CLK
CLK => Q[5]~reg0.CLK
CLK => Q[6]~reg0.CLK
CLK => Q[7]~reg0.CLK
CLK => Q[8]~reg0.CLK
CLK => Q[9]~reg0.CLK
CLK => Q[10]~reg0.CLK
CLK => Q[11]~reg0.CLK
CLK => Q[12]~reg0.CLK
CLK => Q[13]~reg0.CLK
CLK => Q[14]~reg0.CLK
CLK => Q[15]~reg0.CLK
RST => Q[0]~reg0.PRESET
RST => Q[1]~reg0.PRESET
RST => Q[2]~reg0.PRESET
RST => Q[3]~reg0.PRESET
RST => Q[4]~reg0.PRESET
RST => Q[5]~reg0.PRESET
RST => Q[6]~reg0.PRESET
RST => Q[7]~reg0.PRESET
RST => Q[8]~reg0.PRESET
RST => Q[9]~reg0.PRESET
RST => Q[10]~reg0.PRESET
RST => Q[11]~reg0.PRESET
RST => Q[12]~reg0.PRESET
RST => Q[13]~reg0.PRESET
RST => Q[14]~reg0.PRESET
RST => Q[15]~reg0.PRESET
D[0] => Q[0]~reg0.DATAIN
D[1] => Q[1]~reg0.DATAIN
D[2] => Q[2]~reg0.DATAIN
D[3] => Q[3]~reg0.DATAIN
D[4] => Q[4]~reg0.DATAIN
D[5] => Q[5]~reg0.DATAIN
D[6] => Q[6]~reg0.DATAIN
D[7] => Q[7]~reg0.DATAIN
D[8] => Q[8]~reg0.DATAIN
D[9] => Q[9]~reg0.DATAIN
D[10] => Q[10]~reg0.DATAIN
D[11] => Q[11]~reg0.DATAIN
D[12] => Q[12]~reg0.DATAIN
D[13] => Q[13]~reg0.DATAIN
D[14] => Q[14]~reg0.DATAIN
D[15] => Q[15]~reg0.DATAIN
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[10] <= Q[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[11] <= Q[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[12] <= Q[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[13] <= Q[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[14] <= Q[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[15] <= Q[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|part5|seven_segment:u3
c[0] => Mux0.IN19
c[0] => Mux1.IN19
c[0] => Mux2.IN19
c[0] => Mux3.IN19
c[0] => Mux4.IN19
c[0] => Mux5.IN19
c[0] => Mux6.IN19
c[1] => Mux0.IN18
c[1] => Mux1.IN18
c[1] => Mux2.IN18
c[1] => Mux3.IN18
c[1] => Mux4.IN18
c[1] => Mux5.IN18
c[1] => Mux6.IN18
c[2] => Mux0.IN17
c[2] => Mux1.IN17
c[2] => Mux2.IN17
c[2] => Mux3.IN17
c[2] => Mux4.IN17
c[2] => Mux5.IN17
c[2] => Mux6.IN17
c[3] => Mux0.IN16
c[3] => Mux1.IN16
c[3] => Mux2.IN16
c[3] => Mux3.IN16
c[3] => Mux4.IN16
c[3] => Mux5.IN16
c[3] => Mux6.IN16
show[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
show[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
show[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
show[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
show[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
show[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
show[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|part5|seven_segment:u4
c[0] => Mux0.IN19
c[0] => Mux1.IN19
c[0] => Mux2.IN19
c[0] => Mux3.IN19
c[0] => Mux4.IN19
c[0] => Mux5.IN19
c[0] => Mux6.IN19
c[1] => Mux0.IN18
c[1] => Mux1.IN18
c[1] => Mux2.IN18
c[1] => Mux3.IN18
c[1] => Mux4.IN18
c[1] => Mux5.IN18
c[1] => Mux6.IN18
c[2] => Mux0.IN17
c[2] => Mux1.IN17
c[2] => Mux2.IN17
c[2] => Mux3.IN17
c[2] => Mux4.IN17
c[2] => Mux5.IN17
c[2] => Mux6.IN17
c[3] => Mux0.IN16
c[3] => Mux1.IN16
c[3] => Mux2.IN16
c[3] => Mux3.IN16
c[3] => Mux4.IN16
c[3] => Mux5.IN16
c[3] => Mux6.IN16
show[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
show[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
show[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
show[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
show[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
show[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
show[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|part5|seven_segment:u5
c[0] => Mux0.IN19
c[0] => Mux1.IN19
c[0] => Mux2.IN19
c[0] => Mux3.IN19
c[0] => Mux4.IN19
c[0] => Mux5.IN19
c[0] => Mux6.IN19
c[1] => Mux0.IN18
c[1] => Mux1.IN18
c[1] => Mux2.IN18
c[1] => Mux3.IN18
c[1] => Mux4.IN18
c[1] => Mux5.IN18
c[1] => Mux6.IN18
c[2] => Mux0.IN17
c[2] => Mux1.IN17
c[2] => Mux2.IN17
c[2] => Mux3.IN17
c[2] => Mux4.IN17
c[2] => Mux5.IN17
c[2] => Mux6.IN17
c[3] => Mux0.IN16
c[3] => Mux1.IN16
c[3] => Mux2.IN16
c[3] => Mux3.IN16
c[3] => Mux4.IN16
c[3] => Mux5.IN16
c[3] => Mux6.IN16
show[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
show[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
show[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
show[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
show[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
show[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
show[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|part5|seven_segment:u6
c[0] => Mux0.IN19
c[0] => Mux1.IN19
c[0] => Mux2.IN19
c[0] => Mux3.IN19
c[0] => Mux4.IN19
c[0] => Mux5.IN19
c[0] => Mux6.IN19
c[1] => Mux0.IN18
c[1] => Mux1.IN18
c[1] => Mux2.IN18
c[1] => Mux3.IN18
c[1] => Mux4.IN18
c[1] => Mux5.IN18
c[1] => Mux6.IN18
c[2] => Mux0.IN17
c[2] => Mux1.IN17
c[2] => Mux2.IN17
c[2] => Mux3.IN17
c[2] => Mux4.IN17
c[2] => Mux5.IN17
c[2] => Mux6.IN17
c[3] => Mux0.IN16
c[3] => Mux1.IN16
c[3] => Mux2.IN16
c[3] => Mux3.IN16
c[3] => Mux4.IN16
c[3] => Mux5.IN16
c[3] => Mux6.IN16
show[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
show[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
show[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
show[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
show[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
show[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
show[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|part5|seven_segment:u7
c[0] => Mux0.IN19
c[0] => Mux1.IN19
c[0] => Mux2.IN19
c[0] => Mux3.IN19
c[0] => Mux4.IN19
c[0] => Mux5.IN19
c[0] => Mux6.IN19
c[1] => Mux0.IN18
c[1] => Mux1.IN18
c[1] => Mux2.IN18
c[1] => Mux3.IN18
c[1] => Mux4.IN18
c[1] => Mux5.IN18
c[1] => Mux6.IN18
c[2] => Mux0.IN17
c[2] => Mux1.IN17
c[2] => Mux2.IN17
c[2] => Mux3.IN17
c[2] => Mux4.IN17
c[2] => Mux5.IN17
c[2] => Mux6.IN17
c[3] => Mux0.IN16
c[3] => Mux1.IN16
c[3] => Mux2.IN16
c[3] => Mux3.IN16
c[3] => Mux4.IN16
c[3] => Mux5.IN16
c[3] => Mux6.IN16
show[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
show[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
show[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
show[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
show[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
show[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
show[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|part5|seven_segment:u8
c[0] => Mux0.IN19
c[0] => Mux1.IN19
c[0] => Mux2.IN19
c[0] => Mux3.IN19
c[0] => Mux4.IN19
c[0] => Mux5.IN19
c[0] => Mux6.IN19
c[1] => Mux0.IN18
c[1] => Mux1.IN18
c[1] => Mux2.IN18
c[1] => Mux3.IN18
c[1] => Mux4.IN18
c[1] => Mux5.IN18
c[1] => Mux6.IN18
c[2] => Mux0.IN17
c[2] => Mux1.IN17
c[2] => Mux2.IN17
c[2] => Mux3.IN17
c[2] => Mux4.IN17
c[2] => Mux5.IN17
c[2] => Mux6.IN17
c[3] => Mux0.IN16
c[3] => Mux1.IN16
c[3] => Mux2.IN16
c[3] => Mux3.IN16
c[3] => Mux4.IN16
c[3] => Mux5.IN16
c[3] => Mux6.IN16
show[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
show[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
show[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
show[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
show[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
show[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
show[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|part5|seven_segment:u9
c[0] => Mux0.IN19
c[0] => Mux1.IN19
c[0] => Mux2.IN19
c[0] => Mux3.IN19
c[0] => Mux4.IN19
c[0] => Mux5.IN19
c[0] => Mux6.IN19
c[1] => Mux0.IN18
c[1] => Mux1.IN18
c[1] => Mux2.IN18
c[1] => Mux3.IN18
c[1] => Mux4.IN18
c[1] => Mux5.IN18
c[1] => Mux6.IN18
c[2] => Mux0.IN17
c[2] => Mux1.IN17
c[2] => Mux2.IN17
c[2] => Mux3.IN17
c[2] => Mux4.IN17
c[2] => Mux5.IN17
c[2] => Mux6.IN17
c[3] => Mux0.IN16
c[3] => Mux1.IN16
c[3] => Mux2.IN16
c[3] => Mux3.IN16
c[3] => Mux4.IN16
c[3] => Mux5.IN16
c[3] => Mux6.IN16
show[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
show[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
show[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
show[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
show[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
show[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
show[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|part5|seven_segment:u10
c[0] => Mux0.IN19
c[0] => Mux1.IN19
c[0] => Mux2.IN19
c[0] => Mux3.IN19
c[0] => Mux4.IN19
c[0] => Mux5.IN19
c[0] => Mux6.IN19
c[1] => Mux0.IN18
c[1] => Mux1.IN18
c[1] => Mux2.IN18
c[1] => Mux3.IN18
c[1] => Mux4.IN18
c[1] => Mux5.IN18
c[1] => Mux6.IN18
c[2] => Mux0.IN17
c[2] => Mux1.IN17
c[2] => Mux2.IN17
c[2] => Mux3.IN17
c[2] => Mux4.IN17
c[2] => Mux5.IN17
c[2] => Mux6.IN17
c[3] => Mux0.IN16
c[3] => Mux1.IN16
c[3] => Mux2.IN16
c[3] => Mux3.IN16
c[3] => Mux4.IN16
c[3] => Mux5.IN16
c[3] => Mux6.IN16
show[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
show[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
show[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
show[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
show[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
show[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
show[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE