part4.map.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 05 08:23:16 2007 " "Info: Processing started: Tue Jun 05 08:23:16 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "D_latch.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file D_latch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 D_latch-Behavior " "Info: Found design unit 1: D_latch-Behavior" {  } { { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part4/D_latch.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 D_latch " "Info: Found entity 1: D_latch" {  } { { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part4/D_latch.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "low_D_latch.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file low_D_latch.vhd" {  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file part4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 part4-three_D " "Info: Found design unit 1: part4-three_D" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验3/part4/part4.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 part4 " "Info: Found entity 1: part4" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验3/part4/part4.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "part4 " "Info: Elaborating entity \"part4\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "D_latch D_latch:u1 " "Info: Elaborating entity \"D_latch\" for hierarchy \"D_latch:u1\"" {  } { { "part4.vhd" "u1" { Text "E:/VHDL/实验3/part4/part4.vhd" 14 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "Q D_latch.vhd(10) " "Warning (10631): VHDL Process Statement warning at D_latch.vhd(10): inferring latch(es) for signal or variable \"Q\", which holds its previous value in one or more paths through the process" {  } { { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part4/D_latch.vhd" 10 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Q D_latch.vhd(10) " "Info (10041): Verilog HDL or VHDL info at D_latch.vhd(10): inferred latch for \"Q\"" {  } { { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part4/D_latch.vhd" 10 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_LATCH_INFO_HDR" "" "Info: Duplicate LATCH primitives merged into single LATCH primitive" { { "Info" "IOPT_MLS_DUP_LATCH_INFO" "D_latch:u2\|Q D_latch:u1\|Q " "Info: Duplicate LATCH primitive \"D_latch:u2\|Q\" merged with LATCH primitive \"D_latch:u1\|Q\"" {  } { { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part4/D_latch.vhd" 6 -1 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate LATCH primitives merged into single LATCH primitive" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "7 " "Info: Implemented 7 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "2 " "Info: Implemented 2 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 05 08:23:17 2007 " "Info: Processing ended: Tue Jun 05 08:23:17 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}