part4.tan.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "ITDB_TSU_RESULT" "D_latch:u1\|Q D Clock 0.076 ns register " "Info: tsu for register \"D_latch:u1\|Q\" (data pin = \"D\", clock pin = \"Clock\") is 0.076 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.044 ns + Longest pin register " "Info: + Longest pin to register delay is 2.044 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns D 1 PIN PIN_C13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 2; PIN Node = 'D'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { D } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验3/part4/part4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.419 ns) 2.044 ns D_latch:u1\|Q 2 REG LCCOMB_X30_Y35_N8 2 " "Info: 2: + IC(0.646 ns) + CELL(0.419 ns) = 2.044 ns; Loc. = LCCOMB_X30_Y35_N8; Fanout = 2; REG Node = 'D_latch:u1\|Q'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.065 ns" { D D_latch:u1|Q } "NODE_NAME" } } { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part4/D_latch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.398 ns ( 68.40 % ) " "Info: Total cell delay = 1.398 ns ( 68.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.646 ns ( 31.60 % ) " "Info: Total interconnect delay = 0.646 ns ( 31.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.044 ns" { D D_latch:u1|Q } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.044 ns" { D D~combout D_latch:u1|Q } { 0.000ns 0.000ns 0.646ns } { 0.000ns 0.979ns 0.419ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.676 ns + " "Info: + Micro setup delay of destination is 0.676 ns" {  } { { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part4/D_latch.vhd" 6 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 2.644 ns - Shortest register " "Info: - Shortest clock path from clock \"Clock\" to destination register is 2.644 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns Clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'Clock'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验3/part4/part4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns Clock~clkctrl 2 COMB CLKCTRL_G3 2 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 2; COMB Node = 'Clock~clkctrl'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.118 ns" { Clock Clock~clkctrl } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验3/part4/part4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.150 ns) 2.644 ns D_latch:u1\|Q 3 REG LCCOMB_X30_Y35_N8 2 " "Info: 3: + IC(1.377 ns) + CELL(0.150 ns) = 2.644 ns; Loc. = LCCOMB_X30_Y35_N8; Fanout = 2; REG Node = 'D_latch:u1\|Q'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.527 ns" { Clock~clkctrl D_latch:u1|Q } "NODE_NAME" } } { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part4/D_latch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.149 ns ( 43.46 % ) " "Info: Total cell delay = 1.149 ns ( 43.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.495 ns ( 56.54 % ) " "Info: Total interconnect delay = 1.495 ns ( 56.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.644 ns" { Clock Clock~clkctrl D_latch:u1|Q } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.644 ns" { Clock Clock~combout Clock~clkctrl D_latch:u1|Q } { 0.000ns 0.000ns 0.118ns 1.377ns } { 0.000ns 0.999ns 0.000ns 0.150ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.044 ns" { D D_latch:u1|Q } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.044 ns" { D D~combout D_latch:u1|Q } { 0.000ns 0.000ns 0.646ns } { 0.000ns 0.979ns 0.419ns } } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.644 ns" { Clock Clock~clkctrl D_latch:u1|Q } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.644 ns" { Clock Clock~combout Clock~clkctrl D_latch:u1|Q } { 0.000ns 0.000ns 0.118ns 1.377ns } { 0.000ns 0.999ns 0.000ns 0.150ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clock Qa D_latch:u1\|Q 6.266 ns register " "Info: tco from clock \"Clock\" to destination pin \"Qa\" through register \"D_latch:u1\|Q\" is 6.266 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 2.644 ns + Longest register " "Info: + Longest clock path from clock \"Clock\" to source register is 2.644 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns Clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'Clock'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验3/part4/part4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns Clock~clkctrl 2 COMB CLKCTRL_G3 2 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 2; COMB Node = 'Clock~clkctrl'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.118 ns" { Clock Clock~clkctrl } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验3/part4/part4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.150 ns) 2.644 ns D_latch:u1\|Q 3 REG LCCOMB_X30_Y35_N8 2 " "Info: 3: + IC(1.377 ns) + CELL(0.150 ns) = 2.644 ns; Loc. = LCCOMB_X30_Y35_N8; Fanout = 2; REG Node = 'D_latch:u1\|Q'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.527 ns" { Clock~clkctrl D_latch:u1|Q } "NODE_NAME" } } { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part4/D_latch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.149 ns ( 43.46 % ) " "Info: Total cell delay = 1.149 ns ( 43.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.495 ns ( 56.54 % ) " "Info: Total interconnect delay = 1.495 ns ( 56.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.644 ns" { Clock Clock~clkctrl D_latch:u1|Q } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.644 ns" { Clock Clock~combout Clock~clkctrl D_latch:u1|Q } { 0.000ns 0.000ns 0.118ns 1.377ns } { 0.000ns 0.999ns 0.000ns 0.150ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part4/D_latch.vhd" 6 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.622 ns + Longest register pin " "Info: + Longest register to pin delay is 3.622 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns D_latch:u1\|Q 1 REG LCCOMB_X30_Y35_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X30_Y35_N8; Fanout = 2; REG Node = 'D_latch:u1\|Q'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { D_latch:u1|Q } "NODE_NAME" } } { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part4/D_latch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.794 ns) + CELL(2.828 ns) 3.622 ns Qa 2 PIN PIN_J10 0 " "Info: 2: + IC(0.794 ns) + CELL(2.828 ns) = 3.622 ns; Loc. = PIN_J10; Fanout = 0; PIN Node = 'Qa'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.622 ns" { D_latch:u1|Q Qa } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验3/part4/part4.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.828 ns ( 78.08 % ) " "Info: Total cell delay = 2.828 ns ( 78.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.794 ns ( 21.92 % ) " "Info: Total interconnect delay = 0.794 ns ( 21.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.622 ns" { D_latch:u1|Q Qa } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "3.622 ns" { D_latch:u1|Q Qa } { 0.000ns 0.794ns } { 0.000ns 2.828ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.644 ns" { Clock Clock~clkctrl D_latch:u1|Q } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.644 ns" { Clock Clock~combout Clock~clkctrl D_latch:u1|Q } { 0.000ns 0.000ns 0.118ns 1.377ns } { 0.000ns 0.999ns 0.000ns 0.150ns } } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.622 ns" { D_latch:u1|Q Qa } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "3.622 ns" { D_latch:u1|Q Qa } { 0.000ns 0.794ns } { 0.000ns 2.828ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "D_latch:u3\|Q D Clock 0.728 ns register " "Info: th for register \"D_latch:u3\|Q\" (data pin = \"D\", clock pin = \"Clock\") is 0.728 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 2.771 ns + Longest register " "Info: + Longest clock path from clock \"Clock\" to destination register is 2.771 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns Clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'Clock'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验3/part4/part4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns Clock~clkctrl 2 COMB CLKCTRL_G3 2 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 2; COMB Node = 'Clock~clkctrl'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.118 ns" { Clock Clock~clkctrl } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验3/part4/part4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.383 ns) + CELL(0.271 ns) 2.771 ns D_latch:u3\|Q 3 REG LCCOMB_X30_Y35_N26 1 " "Info: 3: + IC(1.383 ns) + CELL(0.271 ns) = 2.771 ns; Loc. = LCCOMB_X30_Y35_N26; Fanout = 1; REG Node = 'D_latch:u3\|Q'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.654 ns" { Clock~clkctrl D_latch:u3|Q } "NODE_NAME" } } { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part4/D_latch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.270 ns ( 45.83 % ) " "Info: Total cell delay = 1.270 ns ( 45.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.501 ns ( 54.17 % ) " "Info: Total interconnect delay = 1.501 ns ( 54.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.771 ns" { Clock Clock~clkctrl D_latch:u3|Q } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.771 ns" { Clock Clock~combout Clock~clkctrl D_latch:u3|Q } { 0.000ns 0.000ns 0.118ns 1.383ns } { 0.000ns 0.999ns 0.000ns 0.271ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part4/D_latch.vhd" 6 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.043 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.043 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns D 1 PIN PIN_C13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 2; PIN Node = 'D'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { D } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验3/part4/part4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.644 ns) + CELL(0.420 ns) 2.043 ns D_latch:u3\|Q 2 REG LCCOMB_X30_Y35_N26 1 " "Info: 2: + IC(0.644 ns) + CELL(0.420 ns) = 2.043 ns; Loc. = LCCOMB_X30_Y35_N26; Fanout = 1; REG Node = 'D_latch:u3\|Q'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.064 ns" { D D_latch:u3|Q } "NODE_NAME" } } { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part4/D_latch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.399 ns ( 68.48 % ) " "Info: Total cell delay = 1.399 ns ( 68.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.644 ns ( 31.52 % ) " "Info: Total interconnect delay = 0.644 ns ( 31.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.043 ns" { D D_latch:u3|Q } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.043 ns" { D D~combout D_latch:u3|Q } { 0.000ns 0.000ns 0.644ns } { 0.000ns 0.979ns 0.420ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.771 ns" { Clock Clock~clkctrl D_latch:u3|Q } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.771 ns" { Clock Clock~combout Clock~clkctrl D_latch:u3|Q } { 0.000ns 0.000ns 0.118ns 1.383ns } { 0.000ns 0.999ns 0.000ns 0.271ns } } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.043 ns" { D D_latch:u3|Q } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "2.043 ns" { D D~combout D_latch:u3|Q } { 0.000ns 0.000ns 0.644ns } { 0.000ns 0.979ns 0.420ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 05 08:23:48 2007 " "Info: Processing ended: Tue Jun 05 08:23:48 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}