part3.tan.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 04 21:43:54 2007 " "Info: Processing started: Mon Jun 04 21:43:54 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off part3 -c part3 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off part3 -c part3 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "D_latch:slave\|Qb " "Info: Node \"D_latch:slave\|Qb\"" {  } { { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part3/D_latch.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0} { "Info" "ITAN_SCC_NODE" "D_latch:slave\|Qa " "Info: Node \"D_latch:slave\|Qa\"" {  } { { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part3/D_latch.vhd" 15 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part3/D_latch.vhd" 9 -1 0 } } { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part3/D_latch.vhd" 15 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "D_latch:master\|Qa " "Info: Node \"D_latch:master\|Qa\"" {  } { { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part3/D_latch.vhd" 15 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0} { "Info" "ITAN_SCC_NODE" "D_latch:master\|Qb " "Info: Node \"D_latch:master\|Qb\"" {  } { { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part3/D_latch.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part3/D_latch.vhd" 15 -1 0 } } { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part3/D_latch.vhd" 9 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "D Q 7.997 ns Longest " "Info: Longest tpd from source pin \"D\" to destination pin \"Q\" is 7.997 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns D 1 PIN PIN_D13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 2; PIN Node = 'D'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { D } "NODE_NAME" } } { "part3.vhd" "" { Text "E:/VHDL/实验3/part3/part3.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.648 ns) + CELL(0.242 ns) 1.869 ns D_latch:master\|R_g 2 COMB LCCOMB_X31_Y35_N28 2 " "Info: 2: + IC(0.648 ns) + CELL(0.242 ns) = 1.869 ns; Loc. = LCCOMB_X31_Y35_N28; Fanout = 2; COMB Node = 'D_latch:master\|R_g'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.890 ns" { D D_latch:master|R_g } "NODE_NAME" } } { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part3/D_latch.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.788 ns) 2.657 ns D_latch:master\|Qa 3 COMB LOOP LCCOMB_X31_Y35_N0 3 " "Info: 3: + IC(0.000 ns) + CELL(0.788 ns) = 2.657 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 3; COMB LOOP Node = 'D_latch:master\|Qa'" { { "Info" "ITDB_PART_OF_SCC" "D_latch:master\|Qa LCCOMB_X31_Y35_N0 " "Info: Loc. = LCCOMB_X31_Y35_N0; Node \"D_latch:master\|Qa\"" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { D_latch:master|Qa } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "D_latch:master\|Qb LCCOMB_X31_Y35_N22 " "Info: Loc. = LCCOMB_X31_Y35_N22; Node \"D_latch:master\|Qb\"" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { D_latch:master|Qb } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { D_latch:master|Qa } "NODE_NAME" } } { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part3/D_latch.vhd" 15 -1 0 } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { D_latch:master|Qb } "NODE_NAME" } } { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part3/D_latch.vhd" 9 -1 0 } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.788 ns" { D_latch:master|R_g D_latch:master|Qa } "NODE_NAME" } } { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part3/D_latch.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.262 ns) + CELL(0.420 ns) 3.339 ns D_latch:slave\|R_g 4 COMB LCCOMB_X31_Y35_N26 2 " "Info: 4: + IC(0.262 ns) + CELL(0.420 ns) = 3.339 ns; Loc. = LCCOMB_X31_Y35_N26; Fanout = 2; COMB Node = 'D_latch:slave\|R_g'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.682 ns" { D_latch:master|Qa D_latch:slave|R_g } "NODE_NAME" } } { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part3/D_latch.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.292 ns) 4.631 ns D_latch:slave\|Qa 5 COMB LOOP LCCOMB_X31_Y35_N2 2 " "Info: 5: + IC(0.000 ns) + CELL(1.292 ns) = 4.631 ns; Loc. = LCCOMB_X31_Y35_N2; Fanout = 2; COMB LOOP Node = 'D_latch:slave\|Qa'" { { "Info" "ITDB_PART_OF_SCC" "D_latch:slave\|Qa LCCOMB_X31_Y35_N2 " "Info: Loc. = LCCOMB_X31_Y35_N2; Node \"D_latch:slave\|Qa\"" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { D_latch:slave|Qa } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "D_latch:slave\|Qb LCCOMB_X31_Y35_N10 " "Info: Loc. = LCCOMB_X31_Y35_N10; Node \"D_latch:slave\|Qb\"" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { D_latch:slave|Qb } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { D_latch:slave|Qa } "NODE_NAME" } } { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part3/D_latch.vhd" 15 -1 0 } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { D_latch:slave|Qb } "NODE_NAME" } } { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part3/D_latch.vhd" 9 -1 0 } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.292 ns" { D_latch:slave|R_g D_latch:slave|Qa } "NODE_NAME" } } { "D_latch.vhd" "" { Text "E:/VHDL/实验3/part3/D_latch.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.578 ns) + CELL(2.788 ns) 7.997 ns Q 6 PIN PIN_B12 0 " "Info: 6: + IC(0.578 ns) + CELL(2.788 ns) = 7.997 ns; Loc. = PIN_B12; Fanout = 0; PIN Node = 'Q'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.366 ns" { D_latch:slave|Qa Q } "NODE_NAME" } } { "part3.vhd" "" { Text "E:/VHDL/实验3/part3/part3.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.509 ns ( 81.39 % ) " "Info: Total cell delay = 6.509 ns ( 81.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.488 ns ( 18.61 % ) " "Info: Total interconnect delay = 1.488 ns ( 18.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "7.997 ns" { D D_latch:master|R_g D_latch:master|Qa D_latch:slave|R_g D_latch:slave|Qa Q } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "7.997 ns" { D D~combout D_latch:master|R_g D_latch:master|Qa D_latch:slave|R_g D_latch:slave|Qa Q } { 0.000ns 0.000ns 0.648ns 0.000ns 0.262ns 0.000ns 0.578ns } { 0.000ns 0.979ns 0.242ns 0.788ns 0.420ns 1.292ns 2.788ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 04 21:43:54 2007 " "Info: Processing ended: Mon Jun 04 21:43:54 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}