part3.hier_info

来自「几个ＶＨＤＬ的编程实例」· HIER_INFO 代码 · 共 24 行

|part3
D => D_latch:master.D
Clock => D_latch:slave.CLk
Clock => D_latch:master.CLk
Q <= D_latch:slave.Q


|part3|D_latch:master
CLk => R_g~0.IN1
CLk => S_g~0.IN1
D => S_g~0.IN0
D => R_g~0.IN0
Q <= Qa.DB_MAX_OUTPUT_PORT_TYPE


|part3|D_latch:slave
CLk => R_g~0.IN1
CLk => S_g~0.IN1
D => S_g~0.IN0
D => R_g~0.IN0
Q <= Qa.DB_MAX_OUTPUT_PORT_TYPE