part2.tan.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 31 01:18:59 2007 " "Info: Processing started: Thu May 31 01:18:59 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off part2 -c part2 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off part2 -c part2 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "Qb " "Info: Node \"Qb\"" {  } { { "part2.vhd" "" { Text "E:/VHDL/实验3/part2/part2.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0} { "Info" "ITAN_SCC_NODE" "Qa " "Info: Node \"Qa\"" {  } { { "part2.vhd" "" { Text "E:/VHDL/实验3/part2/part2.vhd" 17 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "part2.vhd" "" { Text "E:/VHDL/实验3/part2/part2.vhd" 11 -1 0 } } { "part2.vhd" "" { Text "E:/VHDL/实验3/part2/part2.vhd" 17 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "CLk Q 6.547 ns Longest " "Info: Longest tpd from source pin \"CLk\" to destination pin \"Q\" is 6.547 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns CLk 1 PIN PIN_D13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 2; PIN Node = 'CLk'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLk } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验3/part2/part2.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.645 ns) + CELL(0.271 ns) 1.895 ns R_g 2 COMB LCCOMB_X31_Y35_N6 2 " "Info: 2: + IC(0.645 ns) + CELL(0.271 ns) = 1.895 ns; Loc. = LCCOMB_X31_Y35_N6; Fanout = 2; COMB Node = 'R_g'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.916 ns" { CLk R_g } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验3/part2/part2.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.286 ns) 3.181 ns Qa 3 COMB LOOP LCCOMB_X31_Y35_N22 2 " "Info: 3: + IC(0.000 ns) + CELL(1.286 ns) = 3.181 ns; Loc. = LCCOMB_X31_Y35_N22; Fanout = 2; COMB LOOP Node = 'Qa'" { { "Info" "ITDB_PART_OF_SCC" "Qa LCCOMB_X31_Y35_N22 " "Info: Loc. = LCCOMB_X31_Y35_N22; Node \"Qa\"" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { Qa } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "Qb LCCOMB_X31_Y35_N0 " "Info: Loc. = LCCOMB_X31_Y35_N0; Node \"Qb\"" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { Qb } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { Qa } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验3/part2/part2.vhd" 17 -1 0 } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { Qb } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验3/part2/part2.vhd" 11 -1 0 } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.286 ns" { R_g Qa } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验3/part2/part2.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.578 ns) + CELL(2.788 ns) 6.547 ns Q 4 PIN PIN_B12 0 " "Info: 4: + IC(0.578 ns) + CELL(2.788 ns) = 6.547 ns; Loc. = PIN_B12; Fanout = 0; PIN Node = 'Q'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.366 ns" { Qa Q } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验3/part2/part2.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.324 ns ( 81.32 % ) " "Info: Total cell delay = 5.324 ns ( 81.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.223 ns ( 18.68 % ) " "Info: Total interconnect delay = 1.223 ns ( 18.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "6.547 ns" { CLk R_g Qa Q } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "6.547 ns" { CLk CLk~combout R_g Qa Q } { 0.000ns 0.000ns 0.645ns 0.000ns 0.578ns } { 0.000ns 0.979ns 0.271ns 1.286ns 2.788ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 31 01:18:59 2007 " "Info: Processing ended: Thu May 31 01:18:59 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}