part5.map.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 27 17:51:38 2007 " "Info: Processing started: Sun May 27 17:51:38 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part5.vhd 14 7 " "Info: Found 14 design units, including 7 entities, in source file part5.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 part5-Behavior " "Info: Found design unit 1: part5-Behavior" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 mux3b51-Behavior " "Info: Found design unit 2: mux3b51-Behavior" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 segment71-Behavior " "Info: Found design unit 3: segment71-Behavior" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 74 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 segment72-Behavior " "Info: Found design unit 4: segment72-Behavior" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 98 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 segment73-Behavior " "Info: Found design unit 5: segment73-Behavior" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 122 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 segment74-Behavior " "Info: Found design unit 6: segment74-Behavior" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 146 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 segment75-Behavior " "Info: Found design unit 7: segment75-Behavior" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 170 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 part5 " "Info: Found entity 1: part5" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 mux3b51 " "Info: Found entity 2: mux3b51" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 46 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 segment71 " "Info: Found entity 3: segment71" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 70 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 segment72 " "Info: Found entity 4: segment72" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 94 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 segment73 " "Info: Found entity 5: segment73" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 118 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 segment74 " "Info: Found entity 6: segment74" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 142 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 segment75 " "Info: Found entity 7: segment75" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 166 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "part5 " "Info: Elaborating entity \"part5\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux3b51 mux3b51:M0 " "Info: Elaborating entity \"mux3b51\" for hierarchy \"mux3b51:M0\"" {  } { { "part5.vhd" "M0" { Text "E:/VHDL/实验1/part5/part5.vhd" 34 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "U part5.vhd(55) " "Warning (10492): VHDL Process Statement warning at part5.vhd(55): signal \"U\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 55 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "V part5.vhd(56) " "Warning (10492): VHDL Process Statement warning at part5.vhd(56): signal \"V\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 56 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "W part5.vhd(57) " "Warning (10492): VHDL Process Statement warning at part5.vhd(57): signal \"W\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 57 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "X part5.vhd(58) " "Warning (10492): VHDL Process Statement warning at part5.vhd(58): signal \"X\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 58 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Y part5.vhd(59) " "Warning (10492): VHDL Process Statement warning at part5.vhd(59): signal \"Y\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 59 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Y part5.vhd(60) " "Warning (10492): VHDL Process Statement warning at part5.vhd(60): signal \"Y\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 60 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Y part5.vhd(61) " "Warning (10492): VHDL Process Statement warning at part5.vhd(61): signal \"Y\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 61 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Y part5.vhd(62) " "Warning (10492): VHDL Process Statement warning at part5.vhd(62): signal \"Y\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 62 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment71 segment71:H01 " "Info: Elaborating entity \"segment71\" for hierarchy \"segment71:H01\"" {  } { { "part5.vhd" "H01" { Text "E:/VHDL/实验1/part5/part5.vhd" 36 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment72 segment72:H02 " "Info: Elaborating entity \"segment72\" for hierarchy \"segment72:H02\"" {  } { { "part5.vhd" "H02" { Text "E:/VHDL/实验1/part5/part5.vhd" 37 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment73 segment73:H03 " "Info: Elaborating entity \"segment73\" for hierarchy \"segment73:H03\"" {  } { { "part5.vhd" "H03" { Text "E:/VHDL/实验1/part5/part5.vhd" 38 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment74 segment74:H04 " "Info: Elaborating entity \"segment74\" for hierarchy \"segment74:H04\"" {  } { { "part5.vhd" "H04" { Text "E:/VHDL/实验1/part5/part5.vhd" 39 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment75 segment75:H05 " "Info: Elaborating entity \"segment75\" for hierarchy \"segment75:H05\"" {  } { { "part5.vhd" "H05" { Text "E:/VHDL/实验1/part5/part5.vhd" 40 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "79 " "Info: Implemented 79 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "18 " "Info: Implemented 18 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "35 " "Info: Implemented 35 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "26 " "Info: Implemented 26 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 17:51:41 2007 " "Info: Processing ended: Sun May 27 17:51:41 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}