part5.tan.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 27 17:52:02 2007 " "Info: Processing started: Sun May 27 17:52:02 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off part5 -c part5 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off part5 -c part5 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SW\[10\] HEX01\[1\] 15.826 ns Longest " "Info: Longest tpd from source pin \"SW\[10\]\" to destination pin \"HEX01\[1\]\" is 15.826 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.860 ns) 0.860 ns SW\[10\] 1 PIN PIN_AE9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.860 ns) = 0.860 ns; Loc. = PIN_AE9; Fanout = 1; PIN Node = 'SW\[10\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { SW[10] } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.846 ns) + CELL(0.271 ns) 6.977 ns mux3b51:M0\|Mux1~46 2 COMB LCCOMB_X20_Y35_N0 1 " "Info: 2: + IC(5.846 ns) + CELL(0.271 ns) = 6.977 ns; Loc. = LCCOMB_X20_Y35_N0; Fanout = 1; COMB Node = 'mux3b51:M0\|Mux1~46'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "6.117 ns" { SW[10] mux3b51:M0|Mux1~46 } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.248 ns) + CELL(0.150 ns) 7.375 ns mux3b51:M0\|Mux1~47 3 COMB LCCOMB_X20_Y35_N12 4 " "Info: 3: + IC(0.248 ns) + CELL(0.150 ns) = 7.375 ns; Loc. = LCCOMB_X20_Y35_N12; Fanout = 4; COMB Node = 'mux3b51:M0\|Mux1~47'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.398 ns" { mux3b51:M0|Mux1~46 mux3b51:M0|Mux1~47 } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.681 ns) + CELL(0.150 ns) 8.206 ns mux3b51:M0\|Mux1~48 4 COMB LCCOMB_X24_Y35_N10 10 " "Info: 4: + IC(0.681 ns) + CELL(0.150 ns) = 8.206 ns; Loc. = LCCOMB_X24_Y35_N10; Fanout = 10; COMB Node = 'mux3b51:M0\|Mux1~48'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.831 ns" { mux3b51:M0|Mux1~47 mux3b51:M0|Mux1~48 } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.334 ns) + CELL(0.438 ns) 8.978 ns segment71:H01\|Mux2~61 5 COMB LCCOMB_X24_Y35_N24 10 " "Info: 5: + IC(0.334 ns) + CELL(0.438 ns) = 8.978 ns; Loc. = LCCOMB_X24_Y35_N24; Fanout = 10; COMB Node = 'segment71:H01\|Mux2~61'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.772 ns" { mux3b51:M0|Mux1~48 segment71:H01|Mux2~61 } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.060 ns) + CELL(2.788 ns) 15.826 ns HEX01\[1\] 6 PIN PIN_V13 0 " "Info: 6: + IC(4.060 ns) + CELL(2.788 ns) = 15.826 ns; Loc. = PIN_V13; Fanout = 0; PIN Node = 'HEX01\[1\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "6.848 ns" { segment71:H01|Mux2~61 HEX01[1] } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验1/part5/part5.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.657 ns ( 29.43 % ) " "Info: Total cell delay = 4.657 ns ( 29.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.169 ns ( 70.57 % ) " "Info: Total interconnect delay = 11.169 ns ( 70.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "15.826 ns" { SW[10] mux3b51:M0|Mux1~46 mux3b51:M0|Mux1~47 mux3b51:M0|Mux1~48 segment71:H01|Mux2~61 HEX01[1] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "15.826 ns" { SW[10] SW[10]~combout mux3b51:M0|Mux1~46 mux3b51:M0|Mux1~47 mux3b51:M0|Mux1~48 segment71:H01|Mux2~61 HEX01[1] } { 0.000ns 0.000ns 5.846ns 0.248ns 0.681ns 0.334ns 4.060ns } { 0.000ns 0.860ns 0.271ns 0.150ns 0.150ns 0.438ns 2.788ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 17:52:02 2007 " "Info: Processing ended: Sun May 27 17:52:02 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}