part5.hier_info

几个ＶＨＤＬ的编程实例

|part5
SW[0] => mux3b51:M0.Y[0]
SW[1] => mux3b51:M0.Y[1]
SW[2] => mux3b51:M0.Y[2]
SW[3] => mux3b51:M0.X[0]
SW[4] => mux3b51:M0.X[1]
SW[5] => mux3b51:M0.X[2]
SW[6] => mux3b51:M0.W[0]
SW[7] => mux3b51:M0.W[1]
SW[8] => mux3b51:M0.W[2]
SW[9] => mux3b51:M0.V[0]
SW[10] => mux3b51:M0.V[1]
SW[11] => mux3b51:M0.V[2]
SW[12] => mux3b51:M0.U[0]
SW[13] => mux3b51:M0.U[1]
SW[14] => mux3b51:M0.U[2]
SW[15] => mux3b51:M0.S[0]
SW[16] => mux3b51:M0.S[1]
SW[17] => mux3b51:M0.S[2]
HEX01[6] <= segment71:H01.Display[6]
HEX01[5] <= segment71:H01.Display[5]
HEX01[4] <= segment71:H01.Display[4]
HEX01[3] <= segment71:H01.Display[3]
HEX01[2] <= segment71:H01.Display[2]
HEX01[1] <= segment71:H01.Display[1]
HEX01[0] <= segment71:H01.Display[0]
HEX02[6] <= segment72:H02.Display[6]
HEX02[5] <= segment72:H02.Display[5]
HEX02[4] <= segment72:H02.Display[4]
HEX02[3] <= segment72:H02.Display[3]
HEX02[2] <= segment72:H02.Display[2]
HEX02[1] <= segment72:H02.Display[1]
HEX02[0] <= segment72:H02.Display[0]
HEX03[6] <= segment73:H03.Display[6]
HEX03[5] <= segment73:H03.Display[5]
HEX03[4] <= segment73:H03.Display[4]
HEX03[3] <= segment73:H03.Display[3]
HEX03[2] <= segment73:H03.Display[2]
HEX03[1] <= segment73:H03.Display[1]
HEX03[0] <= segment73:H03.Display[0]
HEX04[6] <= segment74:H04.Display[6]
HEX04[5] <= segment74:H04.Display[5]
HEX04[4] <= segment74:H04.Display[4]
HEX04[3] <= segment74:H04.Display[3]
HEX04[2] <= segment74:H04.Display[2]
HEX04[1] <= segment74:H04.Display[1]
HEX04[0] <= segment74:H04.Display[0]
HEX05[6] <= segment75:H05.Display[6]
HEX05[5] <= segment75:H05.Display[5]
HEX05[4] <= segment75:H05.Display[4]
HEX05[3] <= segment75:H05.Display[3]
HEX05[2] <= segment75:H05.Display[2]
HEX05[1] <= segment75:H05.Display[1]
HEX05[0] <= segment75:H05.Display[0]


|part5|mux3b51:M0
S[0] => Mux0.IN2
S[0] => Mux1.IN2
S[0] => Mux2.IN2
S[1] => Mux0.IN1
S[1] => Mux1.IN1
S[1] => Mux2.IN1
S[2] => Mux0.IN0
S[2] => Mux1.IN0
S[2] => Mux2.IN0
U[0] => Mux2.IN3
U[1] => Mux1.IN3
U[2] => Mux0.IN3
V[0] => Mux2.IN4
V[1] => Mux1.IN4
V[2] => Mux0.IN4
W[0] => Mux2.IN5
W[1] => Mux1.IN5
W[2] => Mux0.IN5
X[0] => Mux2.IN6
X[1] => Mux1.IN6
X[2] => Mux0.IN6
Y[0] => Mux2.IN7
Y[0] => Mux2.IN8
Y[0] => Mux2.IN9
Y[0] => Mux2.IN10
Y[1] => Mux1.IN7
Y[1] => Mux1.IN8
Y[1] => Mux1.IN9
Y[1] => Mux1.IN10
Y[2] => Mux0.IN7
Y[2] => Mux0.IN8
Y[2] => Mux0.IN9
Y[2] => Mux0.IN10
M[0] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
M[1] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
M[2] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|part5|segment71:H01
M[0] => Mux1.IN10
M[0] => Mux2.IN10
M[0] => Mux3.IN10
M[0] => Mux4.IN5
M[0] => Mux5.IN5
M[0] => Mux6.IN10
M[1] => Mux0.IN5
M[1] => Mux1.IN9
M[1] => Mux2.IN9
M[1] => Mux3.IN9
M[1] => Mux4.IN4
M[1] => Mux5.IN4
M[1] => Mux6.IN9
M[2] => Mux0.IN4
M[2] => Mux1.IN8
M[2] => Mux2.IN8
M[2] => Mux3.IN8
M[2] => Mux6.IN8
Display[6] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
Display[5] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
Display[4] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
Display[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
Display[2] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
Display[1] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
Display[0] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|part5|segment72:H02
M[0] => Mux0.IN5
M[0] => Mux1.IN10
M[0] => Mux2.IN10
M[0] => Mux3.IN10
M[0] => Mux4.IN10
M[0] => Mux5.IN10
M[1] => Mux0.IN4
M[1] => Mux1.IN9
M[1] => Mux2.IN9
M[1] => Mux3.IN9
M[1] => Mux4.IN9
M[1] => Mux5.IN9
M[2] => Mux1.IN8
M[2] => Mux2.IN8
M[2] => Mux3.IN8
M[2] => Mux4.IN8
M[2] => Mux5.IN8
M[2] => Display[3].DATAIN
Display[6] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
Display[5] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
Display[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
Display[3] <= M[2].DB_MAX_OUTPUT_PORT_TYPE
Display[2] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
Display[1] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
Display[0] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|part5|segment73:H03
M[0] => Mux0.IN10
M[0] => Mux1.IN10
M[0] => Mux2.IN10
M[0] => Mux3.IN10
M[0] => Mux6.IN10
M[1] => Mux0.IN9
M[1] => Mux1.IN9
M[1] => Mux2.IN9
M[1] => Mux3.IN9
M[1] => Mux4.IN5
M[1] => Mux5.IN5
M[1] => Mux6.IN9
M[2] => Mux0.IN8
M[2] => Mux1.IN8
M[2] => Mux2.IN8
M[2] => Mux3.IN8
M[2] => Mux4.IN4
M[2] => Mux5.IN4
M[2] => Mux6.IN8
Display[6] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
Display[5] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
Display[4] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
Display[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
Display[2] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
Display[1] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
Display[0] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|part5|segment74:H04
M[0] => Mux1.IN10
M[0] => Mux2.IN10
M[0] => Mux3.IN10
M[0] => Mux4.IN10
M[0] => Mux5.IN10
M[0] => Mux6.IN5
M[1] => Mux0.IN5
M[1] => Mux1.IN9
M[1] => Mux2.IN9
M[1] => Mux3.IN9
M[1] => Mux4.IN9
M[1] => Mux5.IN9
M[2] => Mux0.IN4
M[2] => Mux1.IN8
M[2] => Mux2.IN8
M[2] => Mux3.IN8
M[2] => Mux4.IN8
M[2] => Mux5.IN8
M[2] => Mux6.IN4
Display[6] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
Display[5] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
Display[4] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
Display[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
Display[2] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
Display[1] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
Display[0] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|part5|segment75:H05
M[0] => Mux0.IN10
M[0] => Mux1.IN10
M[0] => Mux2.IN10
M[0] => Mux3.IN10
M[0] => Mux6.IN5
M[1] => Mux0.IN9
M[1] => Mux1.IN9
M[1] => Mux2.IN9
M[1] => Mux3.IN9
M[1] => Mux4.IN5
M[1] => Mux5.IN5
M[2] => Mux0.IN8
M[2] => Mux1.IN8
M[2] => Mux2.IN8
M[2] => Mux3.IN8
M[2] => Mux4.IN4
M[2] => Mux5.IN4
M[2] => Mux6.IN4
Display[6] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
Display[5] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
Display[4] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
Display[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
Display[2] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
Display[1] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
Display[0] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE