part1.tan.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 26 10:49:46 2007 " "Info: Processing started: Sat May 26 10:49:46 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off DE2 -c part1 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DE2 -c part1 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SW\[8\] LEDR\[8\] 8.892 ns Longest " "Info: Longest tpd from source pin \"SW\[8\]\" to destination pin \"LEDR\[8\]\" is 8.892 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns SW\[8\] 1 PIN PIN_C10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_C10; Fanout = 1; PIN Node = 'SW\[8\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { SW[8] } "NODE_NAME" } } { "part1.vhd" "" { Text "E:/VHDL/实验1/part1/part1.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.284 ns) + CELL(2.768 ns) 8.892 ns LEDR\[8\] 2 PIN PIN_F11 0 " "Info: 2: + IC(5.284 ns) + CELL(2.768 ns) = 8.892 ns; Loc. = PIN_F11; Fanout = 0; PIN Node = 'LEDR\[8\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "8.052 ns" { SW[8] LEDR[8] } "NODE_NAME" } } { "part1.vhd" "" { Text "E:/VHDL/实验1/part1/part1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.608 ns ( 40.58 % ) " "Info: Total cell delay = 3.608 ns ( 40.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.284 ns ( 59.42 % ) " "Info: Total interconnect delay = 5.284 ns ( 59.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "8.892 ns" { SW[8] LEDR[8] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "8.892 ns" { SW[8] SW[8]~combout LEDR[8] } { 0.000ns 0.000ns 5.284ns } { 0.000ns 0.840ns 2.768ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 26 10:49:46 2007 " "Info: Processing ended: Sat May 26 10:49:46 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}