part6.map.qmsg

几个ＶＨＤＬ的编程实例

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Y part6.vhd(78) " "Warning (10492): VHDL Process Statement warning at part6.vhd(78): signal \"Y\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 78 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment70 segment70:H01 " "Info: Elaborating entity \"segment70\" for hierarchy \"segment70:H01\"" {  } { { "part6.vhd" "H01" { Text "E:/VHDL/实验1/part6/part6.vhd" 49 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment71 segment71:H02 " "Info: Elaborating entity \"segment71\" for hierarchy \"segment71:H02\"" {  } { { "part6.vhd" "H02" { Text "E:/VHDL/实验1/part6/part6.vhd" 50 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment72 segment72:H03 " "Info: Elaborating entity \"segment72\" for hierarchy \"segment72:H03\"" {  } { { "part6.vhd" "H03" { Text "E:/VHDL/实验1/part6/part6.vhd" 51 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment73 segment73:H04 " "Info: Elaborating entity \"segment73\" for hierarchy \"segment73:H04\"" {  } { { "part6.vhd" "H04" { Text "E:/VHDL/实验1/part6/part6.vhd" 52 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment74 segment74:H05 " "Info: Elaborating entity \"segment74\" for hierarchy \"segment74:H05\"" {  } { { "part6.vhd" "H05" { Text "E:/VHDL/实验1/part6/part6.vhd" 53 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment75 segment75:H06 " "Info: Elaborating entity \"segment75\" for hierarchy \"segment75:H06\"" {  } { { "part6.vhd" "H06" { Text "E:/VHDL/实验1/part6/part6.vhd" 54 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment76 segment76:H07 " "Info: Elaborating entity \"segment76\" for hierarchy \"segment76:H07\"" {  } { { "part6.vhd" "H07" { Text "E:/VHDL/实验1/part6/part6.vhd" 55 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment77 segment77:H08 " "Info: Elaborating entity \"segment77\" for hierarchy \"segment77:H08\"" {  } { { "part6.vhd" "H08" { Text "E:/VHDL/实验1/part6/part6.vhd" 56 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "15 " "Warning: Design contains 15 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[0\] " "Warning: No output dependent on input pin \"SW\[0\]\"" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[1\] " "Warning: No output dependent on input pin \"SW\[1\]\"" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[2\] " "Warning: No output dependent on input pin \"SW\[2\]\"" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[3\] " "Warning: No output dependent on input pin \"SW\[3\]\"" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[4\] " "Warning: No output dependent on input pin \"SW\[4\]\"" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[5\] " "Warning: No output dependent on input pin \"SW\[5\]\"" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[6\] " "Warning: No output dependent on input pin \"SW\[6\]\"" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[7\] " "Warning: No output dependent on input pin \"SW\[7\]\"" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[8\] " "Warning: No output dependent on input pin \"SW\[8\]\"" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[9\] " "Warning: No output dependent on input pin \"SW\[9\]\"" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[10\] " "Warning: No output dependent on input pin \"SW\[10\]\"" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[11\] " "Warning: No output dependent on input pin \"SW\[11\]\"" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[12\] " "Warning: No output dependent on input pin \"SW\[12\]\"" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[13\] " "Warning: No output dependent on input pin \"SW\[13\]\"" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[14\] " "Warning: No output dependent on input pin \"SW\[14\]\"" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "105 " "Info: Implemented 105 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "18 " "Info: Implemented 18 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "56 " "Info: Implemented 56 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "31 " "Info: Implemented 31 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 25 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jun 02 10:53:01 2007 " "Info: Processing ended: Sat Jun 02 10:53:01 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}