part6.map.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jun 02 10:52:59 2007 " "Info: Processing started: Sat Jun 02 10:52:59 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part6 -c part6 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part6 -c part6" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part6.vhd 20 10 " "Info: Found 20 design units, including 10 entities, in source file part6.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 part6-Behavior " "Info: Found design unit 1: part6-Behavior" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 mux3b51-Behavior " "Info: Found design unit 2: mux3b51-Behavior" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 66 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 segment70-Behavior " "Info: Found design unit 3: segment70-Behavior" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 90 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 segment71-Behavior " "Info: Found design unit 4: segment71-Behavior" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 114 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 segment72-Behavior " "Info: Found design unit 5: segment72-Behavior" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 138 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 segment73-Behavior " "Info: Found design unit 6: segment73-Behavior" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 162 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 segment74-Behavior " "Info: Found design unit 7: segment74-Behavior" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 186 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "8 segment75-Behavior " "Info: Found design unit 8: segment75-Behavior" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 210 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "9 segment76-Behavior " "Info: Found design unit 9: segment76-Behavior" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 234 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "10 segment77-Behavior " "Info: Found design unit 10: segment77-Behavior" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 258 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 part6 " "Info: Found entity 1: part6" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 mux3b51 " "Info: Found entity 2: mux3b51" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 62 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 segment70 " "Info: Found entity 3: segment70" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 86 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 segment71 " "Info: Found entity 4: segment71" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 110 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 segment72 " "Info: Found entity 5: segment72" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 134 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 segment73 " "Info: Found entity 6: segment73" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 158 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 segment74 " "Info: Found entity 7: segment74" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 182 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 segment75 " "Info: Found entity 8: segment75" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 206 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "9 segment76 " "Info: Found entity 9: segment76" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 230 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "10 segment77 " "Info: Found entity 10: segment77" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 254 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "part6 " "Info: Elaborating entity \"part6\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "N part6.vhd(45) " "Warning (10036): Verilog HDL or VHDL warning at part6.vhd(45): object \"N\" assigned a value but never read" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 45 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux3b51 mux3b51:M0 " "Info: Elaborating entity \"mux3b51\" for hierarchy \"mux3b51:M0\"" {  } { { "part6.vhd" "M0" { Text "E:/VHDL/实验1/part6/part6.vhd" 47 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "U part6.vhd(71) " "Warning (10492): VHDL Process Statement warning at part6.vhd(71): signal \"U\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 71 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "V part6.vhd(72) " "Warning (10492): VHDL Process Statement warning at part6.vhd(72): signal \"V\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 72 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "W part6.vhd(73) " "Warning (10492): VHDL Process Statement warning at part6.vhd(73): signal \"W\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 73 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "X part6.vhd(74) " "Warning (10492): VHDL Process Statement warning at part6.vhd(74): signal \"X\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 74 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Y part6.vhd(75) " "Warning (10492): VHDL Process Statement warning at part6.vhd(75): signal \"Y\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 75 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Y part6.vhd(76) " "Warning (10492): VHDL Process Statement warning at part6.vhd(76): signal \"Y\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 76 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Y part6.vhd(77) " "Warning (10492): VHDL Process Statement warning at part6.vhd(77): signal \"Y\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "part6.vhd" "" { Text "E:/VHDL/实验1/part6/part6.vhd" 77 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}