part4.tan.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 27 10:44:05 2007 " "Info: Processing started: Sun May 27 10:44:05 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off part4 -c part4 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off part4 -c part4 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "c\[1\] show\[1\] 9.447 ns Longest " "Info: Longest tpd from source pin \"c\[1\]\" to destination pin \"show\[1\]\" is 9.447 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.870 ns) 0.870 ns c\[1\] 1 PIN PIN_B4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.870 ns) = 0.870 ns; Loc. = PIN_B4; Fanout = 3; PIN Node = 'c\[1\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { c[1] } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验1/part4/part4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.869 ns) + CELL(0.420 ns) 6.159 ns Mux3~18 2 COMB LCCOMB_X1_Y34_N16 2 " "Info: 2: + IC(4.869 ns) + CELL(0.420 ns) = 6.159 ns; Loc. = LCCOMB_X1_Y34_N16; Fanout = 2; COMB Node = 'Mux3~18'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.289 ns" { c[1] Mux3~18 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验1/part4/part4.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(2.662 ns) 9.447 ns show\[1\] 3 PIN PIN_C3 0 " "Info: 3: + IC(0.626 ns) + CELL(2.662 ns) = 9.447 ns; Loc. = PIN_C3; Fanout = 0; PIN Node = 'show\[1\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.288 ns" { Mux3~18 show[1] } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验1/part4/part4.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.952 ns ( 41.83 % ) " "Info: Total cell delay = 3.952 ns ( 41.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.495 ns ( 58.17 % ) " "Info: Total interconnect delay = 5.495 ns ( 58.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "9.447 ns" { c[1] Mux3~18 show[1] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "9.447 ns" { c[1] c[1]~combout Mux3~18 show[1] } { 0.000ns 0.000ns 4.869ns 0.626ns } { 0.000ns 0.870ns 0.420ns 2.662ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 10:44:06 2007 " "Info: Processing ended: Sun May 27 10:44:06 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}