part3.tan.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 27 09:16:28 2007 " "Info: Processing started: Sun May 27 09:16:28 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off part3 -c part3 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off part3 -c part3 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "S\[1\] M\[0\] 10.855 ns Longest " "Info: Longest tpd from source pin \"S\[1\]\" to destination pin \"M\[0\]\" is 10.855 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns S\[1\] 1 PIN PIN_J9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_J9; Fanout = 4; PIN Node = 'S\[1\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { S[1] } "NODE_NAME" } } { "part3.vhd" "" { Text "E:/VHDL/实验1/part3/part3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.098 ns) + CELL(0.438 ns) 6.376 ns mux21a:U4\|M0\[0\]~47 2 COMB LCCOMB_X1_Y35_N22 1 " "Info: 2: + IC(5.098 ns) + CELL(0.438 ns) = 6.376 ns; Loc. = LCCOMB_X1_Y35_N22; Fanout = 1; COMB Node = 'mux21a:U4\|M0\[0\]~47'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.536 ns" { S[1] mux21a:U4|M0[0]~47 } "NODE_NAME" } } { "part3.vhd" "" { Text "E:/VHDL/实验1/part3/part3.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.245 ns) + CELL(0.150 ns) 6.771 ns mux21a:U4\|M0\[0\]~48 3 COMB LCCOMB_X1_Y35_N0 1 " "Info: 3: + IC(0.245 ns) + CELL(0.150 ns) = 6.771 ns; Loc. = LCCOMB_X1_Y35_N0; Fanout = 1; COMB Node = 'mux21a:U4\|M0\[0\]~48'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.395 ns" { mux21a:U4|M0[0]~47 mux21a:U4|M0[0]~48 } "NODE_NAME" } } { "part3.vhd" "" { Text "E:/VHDL/实验1/part3/part3.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.251 ns) + CELL(0.416 ns) 7.438 ns mux21a:U4\|M0\[0\]~49 4 COMB LCCOMB_X1_Y35_N20 1 " "Info: 4: + IC(0.251 ns) + CELL(0.416 ns) = 7.438 ns; Loc. = LCCOMB_X1_Y35_N20; Fanout = 1; COMB Node = 'mux21a:U4\|M0\[0\]~49'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.667 ns" { mux21a:U4|M0[0]~48 mux21a:U4|M0[0]~49 } "NODE_NAME" } } { "part3.vhd" "" { Text "E:/VHDL/实验1/part3/part3.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.755 ns) + CELL(2.662 ns) 10.855 ns M\[0\] 5 PIN PIN_C3 0 " "Info: 5: + IC(0.755 ns) + CELL(2.662 ns) = 10.855 ns; Loc. = PIN_C3; Fanout = 0; PIN Node = 'M\[0\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.417 ns" { mux21a:U4|M0[0]~49 M[0] } "NODE_NAME" } } { "part3.vhd" "" { Text "E:/VHDL/实验1/part3/part3.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.506 ns ( 41.51 % ) " "Info: Total cell delay = 4.506 ns ( 41.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.349 ns ( 58.49 % ) " "Info: Total interconnect delay = 6.349 ns ( 58.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "10.855 ns" { S[1] mux21a:U4|M0[0]~47 mux21a:U4|M0[0]~48 mux21a:U4|M0[0]~49 M[0] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "10.855 ns" { S[1] S[1]~combout mux21a:U4|M0[0]~47 mux21a:U4|M0[0]~48 mux21a:U4|M0[0]~49 M[0] } { 0.000ns 0.000ns 5.098ns 0.245ns 0.251ns 0.755ns } { 0.000ns 0.840ns 0.438ns 0.150ns 0.416ns 2.662ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 09:16:28 2007 " "Info: Processing ended: Sun May 27 09:16:28 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}