part3.hier_info

几个ＶＨＤＬ的编程实例

|part3
U[0] => mux21a:U1.X1[0]
U[1] => mux21a:U1.X1[1]
U[2] => mux21a:U1.X1[2]
V[0] => mux21a:U1.Y1[0]
V[1] => mux21a:U1.Y1[1]
V[2] => mux21a:U1.Y1[2]
W[0] => mux21a:U2.X1[0]
W[1] => mux21a:U2.X1[1]
W[2] => mux21a:U2.X1[2]
X[0] => mux21a:U2.Y1[0]
X[1] => mux21a:U2.Y1[1]
X[2] => mux21a:U2.Y1[2]
Y[0] => mux21a:U4.Y1[0]
Y[1] => mux21a:U4.Y1[1]
Y[2] => mux21a:U4.Y1[2]
S[0] => mux21a:U2.S0
S[0] => mux21a:U1.S0
S[1] => mux21a:U3.S0
S[2] => mux21a:U4.S0
M[0] <= mux21a:U4.M0[0]
M[1] <= mux21a:U4.M0[1]
M[2] <= mux21a:U4.M0[2]


|part3|mux21a:U1
X1[0] => M0~2.DATAB
X1[1] => M0~1.DATAB
X1[2] => M0~0.DATAB
Y1[0] => M0~2.DATAA
Y1[1] => M0~1.DATAA
Y1[2] => M0~0.DATAA
S0 => M0~0.OUTPUTSELECT
S0 => M0~1.OUTPUTSELECT
S0 => M0~2.OUTPUTSELECT
M0[0] <= M0~2.DB_MAX_OUTPUT_PORT_TYPE
M0[1] <= M0~1.DB_MAX_OUTPUT_PORT_TYPE
M0[2] <= M0~0.DB_MAX_OUTPUT_PORT_TYPE


|part3|mux21a:U2
X1[0] => M0~2.DATAB
X1[1] => M0~1.DATAB
X1[2] => M0~0.DATAB
Y1[0] => M0~2.DATAA
Y1[1] => M0~1.DATAA
Y1[2] => M0~0.DATAA
S0 => M0~0.OUTPUTSELECT
S0 => M0~1.OUTPUTSELECT
S0 => M0~2.OUTPUTSELECT
M0[0] <= M0~2.DB_MAX_OUTPUT_PORT_TYPE
M0[1] <= M0~1.DB_MAX_OUTPUT_PORT_TYPE
M0[2] <= M0~0.DB_MAX_OUTPUT_PORT_TYPE


|part3|mux21a:U3
X1[0] => M0~2.DATAB
X1[1] => M0~1.DATAB
X1[2] => M0~0.DATAB
Y1[0] => M0~2.DATAA
Y1[1] => M0~1.DATAA
Y1[2] => M0~0.DATAA
S0 => M0~0.OUTPUTSELECT
S0 => M0~1.OUTPUTSELECT
S0 => M0~2.OUTPUTSELECT
M0[0] <= M0~2.DB_MAX_OUTPUT_PORT_TYPE
M0[1] <= M0~1.DB_MAX_OUTPUT_PORT_TYPE
M0[2] <= M0~0.DB_MAX_OUTPUT_PORT_TYPE


|part3|mux21a:U4
X1[0] => M0~2.DATAB
X1[1] => M0~1.DATAB
X1[2] => M0~0.DATAB
Y1[0] => M0~2.DATAA
Y1[1] => M0~1.DATAA
Y1[2] => M0~0.DATAA
S0 => M0~0.OUTPUTSELECT
S0 => M0~1.OUTPUTSELECT
S0 => M0~2.OUTPUTSELECT
M0[0] <= M0~2.DB_MAX_OUTPUT_PORT_TYPE
M0[1] <= M0~1.DB_MAX_OUTPUT_PORT_TYPE
M0[2] <= M0~0.DB_MAX_OUTPUT_PORT_TYPE