part2.tan.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 26 15:35:47 2007 " "Info: Processing started: Sat May 26 15:35:47 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off part2 -c part2 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off part2 -c part2 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Y\[4\] M\[4\] 9.504 ns Longest " "Info: Longest tpd from source pin \"Y\[4\]\" to destination pin \"M\[4\]\" is 9.504 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns Y\[4\] 1 PIN PIN_V8 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_V8; Fanout = 1; PIN Node = 'Y\[4\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { Y[4] } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验1/part2/part2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.688 ns) + CELL(0.366 ns) 5.141 ns M~84 2 COMB LC_X41_Y1_N6 1 " "Info: 2: + IC(3.688 ns) + CELL(0.366 ns) = 5.141 ns; Loc. = LC_X41_Y1_N6; Fanout = 1; COMB Node = 'M~84'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "4.054 ns" { Y[4] M~84 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验1/part2/part2.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.987 ns) + CELL(2.376 ns) 9.504 ns M\[4\] 3 PIN PIN_W2 0 " "Info: 3: + IC(1.987 ns) + CELL(2.376 ns) = 9.504 ns; Loc. = PIN_W2; Fanout = 0; PIN Node = 'M\[4\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "4.363 ns" { M~84 M[4] } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验1/part2/part2.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.829 ns ( 40.29 % ) " "Info: Total cell delay = 3.829 ns ( 40.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.675 ns ( 59.71 % ) " "Info: Total interconnect delay = 5.675 ns ( 59.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "9.504 ns" { Y[4] M~84 M[4] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "9.504 ns" { Y[4] Y[4]~out0 M~84 M[4] } { 0.000ns 0.000ns 3.688ns 1.987ns } { 0.000ns 1.087ns 0.366ns 2.376ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 26 15:35:47 2007 " "Info: Processing ended: Sat May 26 15:35:47 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}