part5.map.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 03 09:23:23 2007 " "Info: Processing started: Sun Jun 03 09:23:23 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "part5.vhd 24 12 " "Warning: Using design file part5.vhd, which is not specified as a design file for the current project, but contains definitions for 24 design units and 12 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 part5-one " "Info: Found design unit 1: part5-one" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 part4-one " "Info: Found design unit 2: part4-one" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 48 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 part2-one " "Info: Found design unit 3: part2-one" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 88 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 comparator-Com " "Info: Found design unit 4: comparator-Com" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 132 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 mux21-one " "Info: Found design unit 5: mux21-one" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 149 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 mux21a-one " "Info: Found design unit 6: mux21a-one" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 164 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 circuitA-one " "Info: Found design unit 7: circuitA-one" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 177 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "8 four_bit_adder-FA " "Info: Found design unit 8: four_bit_adder-FA" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 197 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "9 f_adder-fd1 " "Info: Found design unit 9: f_adder-fd1" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 217 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "10 circuitB-one " "Info: Found design unit 10: circuitB-one" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 236 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "11 segment7-one " "Info: Found design unit 11: segment7-one" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 258 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "12 segment71-one " "Info: Found design unit 12: segment71-one" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 289 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 part5 " "Info: Found entity 1: part5" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 part4 " "Info: Found entity 2: part4" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 41 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 part2 " "Info: Found entity 3: part2" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 83 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 comparator " "Info: Found entity 4: comparator" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 128 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 mux21 " "Info: Found entity 5: mux21" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 144 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 mux21a " "Info: Found entity 6: mux21a" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 159 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 circuitA " "Info: Found entity 7: circuitA" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 173 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 four_bit_adder " "Info: Found entity 8: four_bit_adder" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 191 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "9 f_adder " "Info: Found entity 9: f_adder" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 213 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "10 circuitB " "Info: Found entity 10: circuitB" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 231 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "11 segment7 " "Info: Found entity 11: segment7" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 253 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "12 segment71 " "Info: Found entity 12: segment71" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 284 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "part5 " "Info: Elaborating entity \"part5\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment71 segment71:unit1 " "Info: Elaborating entity \"segment71\" for hierarchy \"segment71:unit1\"" {  } { { "part5.vhd" "unit1" { Text "E:/VHDL/实验2/part5/part5.vhd" 28 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "part4 part4:unit5 " "Info: Elaborating entity \"part4\" for hierarchy \"part4:unit5\"" {  } { { "part5.vhd" "unit5" { Text "E:/VHDL/实验2/part5/part5.vhd" 32 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "four_bit_adder part4:unit5\|four_bit_adder:add_4bitof2 " "Info: Elaborating entity \"four_bit_adder\" for hierarchy \"part4:unit5\|four_bit_adder:add_4bitof2\"" {  } { { "part5.vhd" "add_4bitof2" { Text "E:/VHDL/实验2/part5/part5.vhd" 72 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "f_adder part4:unit5\|four_bit_adder:add_4bitof2\|f_adder:u1 " "Info: Elaborating entity \"f_adder\" for hierarchy \"part4:unit5\|four_bit_adder:add_4bitof2\|f_adder:u1\"" {  } { { "part5.vhd" "u1" { Text "E:/VHDL/实验2/part5/part5.vhd" 204 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "part2 part4:unit5\|part2:unit1 " "Info: Elaborating entity \"part2\" for hierarchy \"part4:unit5\|part2:unit1\"" {  } { { "part5.vhd" "unit1" { Text "E:/VHDL/实验2/part5/part5.vhd" 73 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "comparator part4:unit5\|part2:unit1\|comparator:u1 " "Info: Elaborating entity \"comparator\" for hierarchy \"part4:unit5\|part2:unit1\|comparator:u1\"" {  } { { "part5.vhd" "u1" { Text "E:/VHDL/实验2/part5/part5.vhd" 110 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux21a part4:unit5\|part2:unit1\|mux21a:u2 " "Info: Elaborating entity \"mux21a\" for hierarchy \"part4:unit5\|part2:unit1\|mux21a:u2\"" {  } { { "part5.vhd" "u2" { Text "E:/VHDL/实验2/part5/part5.vhd" 111 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux21 part4:unit5\|part2:unit1\|mux21:u3 " "Info: Elaborating entity \"mux21\" for hierarchy \"part4:unit5\|part2:unit1\|mux21:u3\"" {  } { { "part5.vhd" "u3" { Text "E:/VHDL/实验2/part5/part5.vhd" 112 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "circuitA part4:unit5\|part2:unit1\|circuitA:u7 " "Info: Elaborating entity \"circuitA\" for hierarchy \"part4:unit5\|part2:unit1\|circuitA:u7\"" {  } { { "part5.vhd" "u7" { Text "E:/VHDL/实验2/part5/part5.vhd" 116 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment7 part4:unit5\|segment7:unit3 " "Info: Elaborating entity \"segment7\" for hierarchy \"part4:unit5\|segment7:unit3\"" {  } { { "part5.vhd" "unit3" { Text "E:/VHDL/实验2/part5/part5.vhd" 76 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "circuitB circuitB:unit7 " "Info: Elaborating entity \"circuitB\" for hierarchy \"circuitB:unit7\"" {  } { { "part5.vhd" "unit7" { Text "E:/VHDL/实验2/part5/part5.vhd" 34 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[4\] GND " "Warning: Pin \"HEX2\[4\]\" stuck at GND" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[5\] GND " "Warning: Pin \"HEX2\[5\]\" stuck at GND" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[6\] VCC " "Warning: Pin \"HEX2\[6\]\" stuck at VCC" {  } { { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "120 " "Info: Implemented 120 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "16 " "Info: Implemented 16 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "49 " "Info: Implemented 49 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "55 " "Info: Implemented 55 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 03 09:23:27 2007 " "Info: Processing ended: Sun Jun 03 09:23:27 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}