part5.tan.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 03 09:24:12 2007 " "Info: Processing started: Sun Jun 03 09:24:12 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off part5 -c part5 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off part5 -c part5 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SW\[8\] HEX1\[0\] 17.285 ns Longest " "Info: Longest tpd from source pin \"SW\[8\]\" to destination pin \"HEX1\[0\]\" is 17.285 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns SW\[8\] 1 PIN PIN_B13 9 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_B13; Fanout = 9; PIN Node = 'SW\[8\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { SW[8] } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.810 ns) + CELL(0.275 ns) 4.084 ns part4:unit5\|four_bit_adder:add_4bitof2\|f_adder:u2\|co~43 2 COMB LCCOMB_X7_Y14_N24 2 " "Info: 2: + IC(2.810 ns) + CELL(0.275 ns) = 4.084 ns; Loc. = LCCOMB_X7_Y14_N24; Fanout = 2; COMB Node = 'part4:unit5\|four_bit_adder:add_4bitof2\|f_adder:u2\|co~43'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.085 ns" { SW[8] part4:unit5|four_bit_adder:add_4bitof2|f_adder:u2|co~43 } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 215 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.275 ns) 4.613 ns part4:unit5\|four_bit_adder:add_4bitof2\|f_adder:u3\|co~77 3 COMB LCCOMB_X7_Y14_N26 2 " "Info: 3: + IC(0.254 ns) + CELL(0.275 ns) = 4.613 ns; Loc. = LCCOMB_X7_Y14_N26; Fanout = 2; COMB Node = 'part4:unit5\|four_bit_adder:add_4bitof2\|f_adder:u3\|co~77'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.529 ns" { part4:unit5|four_bit_adder:add_4bitof2|f_adder:u2|co~43 part4:unit5|four_bit_adder:add_4bitof2|f_adder:u3|co~77 } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 215 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.248 ns) + CELL(0.150 ns) 5.011 ns part4:unit5\|four_bit_adder:add_4bitof2\|f_adder:u4\|co~126 4 COMB LCCOMB_X7_Y14_N6 6 " "Info: 4: + IC(0.248 ns) + CELL(0.150 ns) = 5.011 ns; Loc. = LCCOMB_X7_Y14_N6; Fanout = 6; COMB Node = 'part4:unit5\|four_bit_adder:add_4bitof2\|f_adder:u4\|co~126'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.398 ns" { part4:unit5|four_bit_adder:add_4bitof2|f_adder:u3|co~77 part4:unit5|four_bit_adder:add_4bitof2|f_adder:u4|co~126 } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 215 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.137 ns) + CELL(0.438 ns) 6.586 ns part4:unit6\|four_bit_adder:add_4bitof2\|f_adder:u1\|co~10 5 COMB LCCOMB_X1_Y15_N16 2 " "Info: 5: + IC(1.137 ns) + CELL(0.438 ns) = 6.586 ns; Loc. = LCCOMB_X1_Y15_N16; Fanout = 2; COMB Node = 'part4:unit6\|four_bit_adder:add_4bitof2\|f_adder:u1\|co~10'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.575 ns" { part4:unit5|four_bit_adder:add_4bitof2|f_adder:u4|co~126 part4:unit6|four_bit_adder:add_4bitof2|f_adder:u1|co~10 } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 215 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.587 ns) + CELL(0.420 ns) 9.593 ns part4:unit6\|four_bit_adder:add_4bitof2\|f_adder:u2\|co~10 6 COMB LCCOMB_X33_Y6_N10 2 " "Info: 6: + IC(2.587 ns) + CELL(0.420 ns) = 9.593 ns; Loc. = LCCOMB_X33_Y6_N10; Fanout = 2; COMB Node = 'part4:unit6\|four_bit_adder:add_4bitof2\|f_adder:u2\|co~10'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.007 ns" { part4:unit6|four_bit_adder:add_4bitof2|f_adder:u1|co~10 part4:unit6|four_bit_adder:add_4bitof2|f_adder:u2|co~10 } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 215 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.277 ns) + CELL(0.150 ns) 10.020 ns part4:unit6\|four_bit_adder:add_4bitof2\|f_adder:u3\|co~10 7 COMB LCCOMB_X33_Y6_N2 3 " "Info: 7: + IC(0.277 ns) + CELL(0.150 ns) = 10.020 ns; Loc. = LCCOMB_X33_Y6_N2; Fanout = 3; COMB Node = 'part4:unit6\|four_bit_adder:add_4bitof2\|f_adder:u3\|co~10'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.427 ns" { part4:unit6|four_bit_adder:add_4bitof2|f_adder:u2|co~10 part4:unit6|four_bit_adder:add_4bitof2|f_adder:u3|co~10 } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 215 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.256 ns) + CELL(0.150 ns) 10.426 ns part4:unit6\|four_bit_adder:add_4bitof2\|f_adder:u4\|co~10 8 COMB LCCOMB_X33_Y6_N22 5 " "Info: 8: + IC(0.256 ns) + CELL(0.150 ns) = 10.426 ns; Loc. = LCCOMB_X33_Y6_N22; Fanout = 5; COMB Node = 'part4:unit6\|four_bit_adder:add_4bitof2\|f_adder:u4\|co~10'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.406 ns" { part4:unit6|four_bit_adder:add_4bitof2|f_adder:u3|co~10 part4:unit6|four_bit_adder:add_4bitof2|f_adder:u4|co~10 } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 215 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.275 ns) 11.201 ns part4:unit6\|part2:unit1\|mux21:u4\|y~58 9 COMB LCCOMB_X33_Y6_N26 7 " "Info: 9: + IC(0.500 ns) + CELL(0.275 ns) = 11.201 ns; Loc. = LCCOMB_X33_Y6_N26; Fanout = 7; COMB Node = 'part4:unit6\|part2:unit1\|mux21:u4\|y~58'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.775 ns" { part4:unit6|four_bit_adder:add_4bitof2|f_adder:u4|co~10 part4:unit6|part2:unit1|mux21:u4|y~58 } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 147 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.316 ns) + CELL(0.416 ns) 11.933 ns part4:unit6\|segment7:unit3\|Mux6~6 10 COMB LCCOMB_X33_Y6_N18 1 " "Info: 10: + IC(0.316 ns) + CELL(0.416 ns) = 11.933 ns; Loc. = LCCOMB_X33_Y6_N18; Fanout = 1; COMB Node = 'part4:unit6\|segment7:unit3\|Mux6~6'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.732 ns" { part4:unit6|part2:unit1|mux21:u4|y~58 part4:unit6|segment7:unit3|Mux6~6 } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 262 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.563 ns) + CELL(2.789 ns) 17.285 ns HEX1\[0\] 11 PIN PIN_V20 0 " "Info: 11: + IC(2.563 ns) + CELL(2.789 ns) = 17.285 ns; Loc. = PIN_V20; Fanout = 0; PIN Node = 'HEX1\[0\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.352 ns" { part4:unit6|segment7:unit3|Mux6~6 HEX1[0] } "NODE_NAME" } } { "part5.vhd" "" { Text "E:/VHDL/实验2/part5/part5.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.337 ns ( 36.66 % ) " "Info: Total cell delay = 6.337 ns ( 36.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.948 ns ( 63.34 % ) " "Info: Total interconnect delay = 10.948 ns ( 63.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "17.285 ns" { SW[8] part4:unit5|four_bit_adder:add_4bitof2|f_adder:u2|co~43 part4:unit5|four_bit_adder:add_4bitof2|f_adder:u3|co~77 part4:unit5|four_bit_adder:add_4bitof2|f_adder:u4|co~126 part4:unit6|four_bit_adder:add_4bitof2|f_adder:u1|co~10 part4:unit6|four_bit_adder:add_4bitof2|f_adder:u2|co~10 part4:unit6|four_bit_adder:add_4bitof2|f_adder:u3|co~10 part4:unit6|four_bit_adder:add_4bitof2|f_adder:u4|co~10 part4:unit6|part2:unit1|mux21:u4|y~58 part4:unit6|segment7:unit3|Mux6~6 HEX1[0] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "17.285 ns" { SW[8] SW[8]~combout part4:unit5|four_bit_adder:add_4bitof2|f_adder:u2|co~43 part4:unit5|four_bit_adder:add_4bitof2|f_adder:u3|co~77 part4:unit5|four_bit_adder:add_4bitof2|f_adder:u4|co~126 part4:unit6|four_bit_adder:add_4bitof2|f_adder:u1|co~10 part4:unit6|four_bit_adder:add_4bitof2|f_adder:u2|co~10 part4:unit6|four_bit_adder:add_4bitof2|f_adder:u3|co~10 part4:unit6|four_bit_adder:add_4bitof2|f_adder:u4|co~10 part4:unit6|part2:unit1|mux21:u4|y~58 part4:unit6|segment7:unit3|Mux6~6 HEX1[0] } { 0.000ns 0.000ns 2.810ns 0.254ns 0.248ns 1.137ns 2.587ns 0.277ns 0.256ns 0.500ns 0.316ns 2.563ns } { 0.000ns 0.999ns 0.275ns 0.275ns 0.150ns 0.438ns 0.420ns 0.150ns 0.150ns 0.275ns 0.416ns 2.789ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 03 09:24:12 2007 " "Info: Processing ended: Sun Jun 03 09:24:12 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}