part5.hier_info

几个ＶＨＤＬ的编程实例

|part5
SW[0] => part4:unit5.X2[0]
SW[0] => segment71:unit3.Q[0]
SW[1] => part4:unit5.X2[1]
SW[1] => segment71:unit3.Q[1]
SW[2] => part4:unit5.X2[2]
SW[2] => segment71:unit3.Q[2]
SW[3] => part4:unit5.X2[3]
SW[3] => segment71:unit3.Q[3]
SW[4] => part4:unit6.X2[0]
SW[4] => segment71:unit4.Q[0]
SW[5] => part4:unit6.X2[1]
SW[5] => segment71:unit4.Q[1]
SW[6] => part4:unit6.X2[2]
SW[6] => segment71:unit4.Q[2]
SW[7] => part4:unit6.X2[3]
SW[7] => segment71:unit4.Q[3]
SW[8] => part4:unit5.X1[0]
SW[8] => segment71:unit1.Q[0]
SW[9] => part4:unit5.X1[1]
SW[9] => segment71:unit1.Q[1]
SW[10] => part4:unit5.X1[2]
SW[10] => segment71:unit1.Q[2]
SW[11] => part4:unit5.X1[3]
SW[11] => segment71:unit1.Q[3]
SW[12] => part4:unit6.X1[0]
SW[12] => segment71:unit2.Q[0]
SW[13] => part4:unit6.X1[1]
SW[13] => segment71:unit2.Q[1]
SW[14] => part4:unit6.X1[2]
SW[14] => segment71:unit2.Q[2]
SW[15] => part4:unit6.X1[3]
SW[15] => segment71:unit2.Q[3]
HEX0[0] <= part4:unit5.d0[0]
HEX0[1] <= part4:unit5.d0[1]
HEX0[2] <= part4:unit5.d0[2]
HEX0[3] <= part4:unit5.d0[3]
HEX0[4] <= part4:unit5.d0[4]
HEX0[5] <= part4:unit5.d0[5]
HEX0[6] <= part4:unit5.d0[6]
HEX1[0] <= part4:unit6.d0[0]
HEX1[1] <= part4:unit6.d0[1]
HEX1[2] <= part4:unit6.d0[2]
HEX1[3] <= part4:unit6.d0[3]
HEX1[4] <= part4:unit6.d0[4]
HEX1[5] <= part4:unit6.d0[5]
HEX1[6] <= part4:unit6.d0[6]
HEX2[0] <= circuitB:unit7.show[0]
HEX2[1] <= circuitB:unit7.show[1]
HEX2[2] <= circuitB:unit7.show[2]
HEX2[3] <= circuitB:unit7.show[3]
HEX2[4] <= circuitB:unit7.show[4]
HEX2[5] <= circuitB:unit7.show[5]
HEX2[6] <= circuitB:unit7.show[6]
HEX4[0] <= segment71:unit3.display1[0]
HEX4[1] <= segment71:unit3.display1[1]
HEX4[2] <= segment71:unit3.display1[2]
HEX4[3] <= segment71:unit3.display1[3]
HEX4[4] <= segment71:unit3.display1[4]
HEX4[5] <= segment71:unit3.display1[5]
HEX4[6] <= segment71:unit3.display1[6]
HEX5[0] <= segment71:unit4.display1[0]
HEX5[1] <= segment71:unit4.display1[1]
HEX5[2] <= segment71:unit4.display1[2]
HEX5[3] <= segment71:unit4.display1[3]
HEX5[4] <= segment71:unit4.display1[4]
HEX5[5] <= segment71:unit4.display1[5]
HEX5[6] <= segment71:unit4.display1[6]
HEX6[0] <= segment71:unit1.display1[0]
HEX6[1] <= segment71:unit1.display1[1]
HEX6[2] <= segment71:unit1.display1[2]
HEX6[3] <= segment71:unit1.display1[3]
HEX6[4] <= segment71:unit1.display1[4]
HEX6[5] <= segment71:unit1.display1[5]
HEX6[6] <= segment71:unit1.display1[6]
HEX7[0] <= segment71:unit2.display1[0]
HEX7[1] <= segment71:unit2.display1[1]
HEX7[2] <= segment71:unit2.display1[2]
HEX7[3] <= segment71:unit2.display1[3]
HEX7[4] <= segment71:unit2.display1[4]
HEX7[5] <= segment71:unit2.display1[5]
HEX7[6] <= segment71:unit2.display1[6]


|part5|segment71:unit1
Q[0] => Mux0.IN19
Q[0] => Mux1.IN19
Q[0] => Mux2.IN19
Q[0] => Mux3.IN19
Q[0] => Mux4.IN19
Q[0] => Mux5.IN19
Q[0] => Mux6.IN19
Q[1] => Mux0.IN18
Q[1] => Mux1.IN18
Q[1] => Mux2.IN18
Q[1] => Mux3.IN18
Q[1] => Mux4.IN18
Q[1] => Mux5.IN18
Q[1] => Mux6.IN18
Q[2] => Mux0.IN17
Q[2] => Mux1.IN17
Q[2] => Mux2.IN17
Q[2] => Mux3.IN17
Q[2] => Mux4.IN17
Q[2] => Mux5.IN17
Q[2] => Mux6.IN17
Q[3] => Mux0.IN16
Q[3] => Mux1.IN16
Q[3] => Mux2.IN16
Q[3] => Mux3.IN16
Q[3] => Mux4.IN16
Q[3] => Mux5.IN16
Q[3] => Mux6.IN16
display1[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
display1[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
display1[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
display1[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
display1[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
display1[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
display1[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|part5|segment71:unit2
Q[0] => Mux0.IN19
Q[0] => Mux1.IN19
Q[0] => Mux2.IN19
Q[0] => Mux3.IN19
Q[0] => Mux4.IN19
Q[0] => Mux5.IN19
Q[0] => Mux6.IN19
Q[1] => Mux0.IN18
Q[1] => Mux1.IN18
Q[1] => Mux2.IN18
Q[1] => Mux3.IN18
Q[1] => Mux4.IN18
Q[1] => Mux5.IN18
Q[1] => Mux6.IN18
Q[2] => Mux0.IN17
Q[2] => Mux1.IN17
Q[2] => Mux2.IN17
Q[2] => Mux3.IN17
Q[2] => Mux4.IN17
Q[2] => Mux5.IN17
Q[2] => Mux6.IN17
Q[3] => Mux0.IN16
Q[3] => Mux1.IN16
Q[3] => Mux2.IN16
Q[3] => Mux3.IN16
Q[3] => Mux4.IN16
Q[3] => Mux5.IN16
Q[3] => Mux6.IN16
display1[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
display1[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
display1[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
display1[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
display1[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
display1[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
display1[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|part5|segment71:unit3
Q[0] => Mux0.IN19
Q[0] => Mux1.IN19
Q[0] => Mux2.IN19
Q[0] => Mux3.IN19
Q[0] => Mux4.IN19
Q[0] => Mux5.IN19
Q[0] => Mux6.IN19
Q[1] => Mux0.IN18
Q[1] => Mux1.IN18
Q[1] => Mux2.IN18
Q[1] => Mux3.IN18
Q[1] => Mux4.IN18
Q[1] => Mux5.IN18
Q[1] => Mux6.IN18
Q[2] => Mux0.IN17
Q[2] => Mux1.IN17
Q[2] => Mux2.IN17
Q[2] => Mux3.IN17
Q[2] => Mux4.IN17
Q[2] => Mux5.IN17
Q[2] => Mux6.IN17
Q[3] => Mux0.IN16
Q[3] => Mux1.IN16
Q[3] => Mux2.IN16
Q[3] => Mux3.IN16
Q[3] => Mux4.IN16
Q[3] => Mux5.IN16
Q[3] => Mux6.IN16
display1[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
display1[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
display1[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
display1[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
display1[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
display1[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
display1[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|part5|segment71:unit4
Q[0] => Mux0.IN19
Q[0] => Mux1.IN19
Q[0] => Mux2.IN19
Q[0] => Mux3.IN19
Q[0] => Mux4.IN19
Q[0] => Mux5.IN19
Q[0] => Mux6.IN19
Q[1] => Mux0.IN18
Q[1] => Mux1.IN18
Q[1] => Mux2.IN18
Q[1] => Mux3.IN18
Q[1] => Mux4.IN18
Q[1] => Mux5.IN18
Q[1] => Mux6.IN18
Q[2] => Mux0.IN17
Q[2] => Mux1.IN17
Q[2] => Mux2.IN17
Q[2] => Mux3.IN17
Q[2] => Mux4.IN17
Q[2] => Mux5.IN17
Q[2] => Mux6.IN17
Q[3] => Mux0.IN16
Q[3] => Mux1.IN16
Q[3] => Mux2.IN16
Q[3] => Mux3.IN16
Q[3] => Mux4.IN16
Q[3] => Mux5.IN16
Q[3] => Mux6.IN16
display1[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
display1[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
display1[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
display1[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
display1[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
display1[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
display1[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|part5|part4:unit5
X1[0] => four_bit_adder:add_4bitof2.a1[0]
X1[1] => four_bit_adder:add_4bitof2.a1[1]
X1[2] => four_bit_adder:add_4bitof2.a1[2]
X1[3] => four_bit_adder:add_4bitof2.a1[3]
X2[0] => four_bit_adder:add_4bitof2.b[0]
X2[1] => four_bit_adder:add_4bitof2.b[1]
X2[2] => four_bit_adder:add_4bitof2.b[2]
X2[3] => four_bit_adder:add_4bitof2.b[3]
CI => four_bit_adder:add_4bitof2.Cin
d0[0] <= segment7:unit3.display[0]
d0[1] <= segment7:unit3.display[1]
d0[2] <= segment7:unit3.display[2]
d0[3] <= segment7:unit3.display[3]
d0[4] <= segment7:unit3.display[4]
d0[5] <= segment7:unit3.display[5]
d0[6] <= segment7:unit3.display[6]
cou <= cou~0


|part5|part4:unit5|four_bit_adder:add_4bitof2
a1[0] => f_adder:u1.ao
a1[1] => f_adder:u2.ao
a1[2] => f_adder:u3.ao
a1[3] => f_adder:u4.ao
b[0] => f_adder:u1.bo
b[1] => f_adder:u2.bo
b[2] => f_adder:u3.bo
b[3] => f_adder:u4.bo
Cin => f_adder:u1.c
s[0] <= f_adder:u1.so
s[1] <= f_adder:u2.so
s[2] <= f_adder:u3.so
s[3] <= f_adder:u4.so
Cout <= f_adder:u4.co


|part5|part4:unit5|four_bit_adder:add_4bitof2|f_adder:u1
ao => d.IN0
bo => d.IN1
bo => co~0.DATAA
c => so~0.IN0
c => co~0.DATAB
so <= so~0.DB_MAX_OUTPUT_PORT_TYPE
co <= co~0.DB_MAX_OUTPUT_PORT_TYPE


|part5|part4:unit5|four_bit_adder:add_4bitof2|f_adder:u2
ao => d.IN0
bo => d.IN1
bo => co~0.DATAA
c => so~0.IN0
c => co~0.DATAB
so <= so~0.DB_MAX_OUTPUT_PORT_TYPE
co <= co~0.DB_MAX_OUTPUT_PORT_TYPE


|part5|part4:unit5|four_bit_adder:add_4bitof2|f_adder:u3
ao => d.IN0
bo => d.IN1
bo => co~0.DATAA
c => so~0.IN0
c => co~0.DATAB
so <= so~0.DB_MAX_OUTPUT_PORT_TYPE
co <= co~0.DB_MAX_OUTPUT_PORT_TYPE


|part5|part4:unit5|four_bit_adder:add_4bitof2|f_adder:u4
ao => d.IN0
bo => d.IN1
bo => co~0.DATAA
c => so~0.IN0
c => co~0.DATAB
so <= so~0.DB_MAX_OUTPUT_PORT_TYPE
co <= co~0.DB_MAX_OUTPUT_PORT_TYPE


|part5|part4:unit5|part2:unit1
V[0] => circuitA:u7.p[0]
V[0] => mux21:u6.a
V[0] => comparator:u1.A[0]
V[1] => circuitA:u7.p[1]
V[1] => mux21:u5.a
V[1] => comparator:u1.A[1]
V[2] => circuitA:u7.p[2]
V[2] => mux21:u4.a
V[2] => comparator:u1.A[2]
V[3] => circuitA:u7.p[3]
V[3] => mux21:u3.a
V[3] => comparator:u1.A[3]
V[4] => mux21a:u2.a