part4.map.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display\[2\] part4.vhd(221) " "Info (10041): Verilog HDL or VHDL info at part4.vhd(221): inferred latch for \"display\[2\]\"" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display\[3\] part4.vhd(221) " "Info (10041): Verilog HDL or VHDL info at part4.vhd(221): inferred latch for \"display\[3\]\"" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display\[4\] part4.vhd(221) " "Info (10041): Verilog HDL or VHDL info at part4.vhd(221): inferred latch for \"display\[4\]\"" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display\[5\] part4.vhd(221) " "Info (10041): Verilog HDL or VHDL info at part4.vhd(221): inferred latch for \"display\[5\]\"" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display\[6\] part4.vhd(221) " "Info (10041): Verilog HDL or VHDL info at part4.vhd(221): inferred latch for \"display\[6\]\"" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "segment7:unit3\|display\[0\] " "Warning: Latch segment7:unit3\|display\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA SW\[8\] " "Warning: Ports D and ENA on the latch are fed by the same signal SW\[8\]" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "segment7:unit3\|display\[1\] " "Warning: Latch segment7:unit3\|display\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA SW\[8\] " "Warning: Ports D and ENA on the latch are fed by the same signal SW\[8\]" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "segment7:unit3\|display\[2\] " "Warning: Latch segment7:unit3\|display\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA SW\[8\] " "Warning: Ports D and ENA on the latch are fed by the same signal SW\[8\]" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "segment7:unit3\|display\[3\] " "Warning: Latch segment7:unit3\|display\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA SW\[8\] " "Warning: Ports D and ENA on the latch are fed by the same signal SW\[8\]" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "segment7:unit3\|display\[4\] " "Warning: Latch segment7:unit3\|display\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA SW\[8\] " "Warning: Ports D and ENA on the latch are fed by the same signal SW\[8\]" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "segment7:unit3\|display\[5\] " "Warning: Latch segment7:unit3\|display\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA four_bit_adder:add_4bitof2\|f_adder:u2\|d " "Warning: Ports D and ENA on the latch are fed by the same signal four_bit_adder:add_4bitof2\|f_adder:u2\|d" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 179 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "segment7:unit3\|display\[6\] " "Warning: Latch segment7:unit3\|display\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA SW\[8\] " "Warning: Ports D and ENA on the latch are fed by the same signal SW\[8\]" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[4\] GND " "Warning: Pin \"HEX1\[4\]\" stuck at GND" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[5\] GND " "Warning: Pin \"HEX1\[5\]\" stuck at GND" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[6\] VCC " "Warning: Pin \"HEX1\[6\]\" stuck at VCC" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "48 " "Info: Implemented 48 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "25 " "Info: Implemented 25 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 19 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 03 09:48:23 2007 " "Info: Processing ended: Sun Jun 03 09:48:23 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}