part4.map.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 03 09:48:21 2007 " "Info: Processing started: Sun Jun 03 09:48:21 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part4.vhd 20 10 " "Info: Found 20 design units, including 10 entities, in source file part4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 part4-one " "Info: Found design unit 1: part4-one" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 part2-one " "Info: Found design unit 2: part2-one" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 comparator-Com " "Info: Found design unit 3: comparator-Com" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 93 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 mux21-one " "Info: Found design unit 4: mux21-one" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 110 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 mux21a-one " "Info: Found design unit 5: mux21a-one" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 125 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 circuitA-one " "Info: Found design unit 6: circuitA-one" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 138 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 four_bit_adder-FA " "Info: Found design unit 7: four_bit_adder-FA" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 158 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "8 f_adder-fd1 " "Info: Found design unit 8: f_adder-fd1" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 178 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "9 circuitB-one " "Info: Found design unit 9: circuitB-one" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 197 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "10 segment7-one " "Info: Found design unit 10: segment7-one" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 219 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 part4 " "Info: Found entity 1: part4" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 part2 " "Info: Found entity 2: part2" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 44 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 comparator " "Info: Found entity 3: comparator" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 89 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 mux21 " "Info: Found entity 4: mux21" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 105 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 mux21a " "Info: Found entity 5: mux21a" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 120 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 circuitA " "Info: Found entity 6: circuitA" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 134 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 four_bit_adder " "Info: Found entity 7: four_bit_adder" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 152 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 f_adder " "Info: Found entity 8: f_adder" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 174 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "9 circuitB " "Info: Found entity 9: circuitB" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 192 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "10 segment7 " "Info: Found entity 10: segment7" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 214 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "part4 " "Info: Elaborating entity \"part4\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "four_bit_adder four_bit_adder:add_4bitof2 " "Info: Elaborating entity \"four_bit_adder\" for hierarchy \"four_bit_adder:add_4bitof2\"" {  } { { "part4.vhd" "add_4bitof2" { Text "E:/VHDL/实验2/part4/part4.vhd" 33 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "f_adder four_bit_adder:add_4bitof2\|f_adder:u1 " "Info: Elaborating entity \"f_adder\" for hierarchy \"four_bit_adder:add_4bitof2\|f_adder:u1\"" {  } { { "part4.vhd" "u1" { Text "E:/VHDL/实验2/part4/part4.vhd" 165 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "part2 part2:unit1 " "Info: Elaborating entity \"part2\" for hierarchy \"part2:unit1\"" {  } { { "part4.vhd" "unit1" { Text "E:/VHDL/实验2/part4/part4.vhd" 34 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "comparator part2:unit1\|comparator:u1 " "Info: Elaborating entity \"comparator\" for hierarchy \"part2:unit1\|comparator:u1\"" {  } { { "part4.vhd" "u1" { Text "E:/VHDL/实验2/part4/part4.vhd" 71 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux21a part2:unit1\|mux21a:u2 " "Info: Elaborating entity \"mux21a\" for hierarchy \"part2:unit1\|mux21a:u2\"" {  } { { "part4.vhd" "u2" { Text "E:/VHDL/实验2/part4/part4.vhd" 72 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux21 part2:unit1\|mux21:u3 " "Info: Elaborating entity \"mux21\" for hierarchy \"part2:unit1\|mux21:u3\"" {  } { { "part4.vhd" "u3" { Text "E:/VHDL/实验2/part4/part4.vhd" 73 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "circuitA part2:unit1\|circuitA:u7 " "Info: Elaborating entity \"circuitA\" for hierarchy \"part2:unit1\|circuitA:u7\"" {  } { { "part4.vhd" "u7" { Text "E:/VHDL/实验2/part4/part4.vhd" 77 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "circuitB circuitB:unit2 " "Info: Elaborating entity \"circuitB\" for hierarchy \"circuitB:unit2\"" {  } { { "part4.vhd" "unit2" { Text "E:/VHDL/实验2/part4/part4.vhd" 36 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment7 segment7:unit3 " "Info: Elaborating entity \"segment7\" for hierarchy \"segment7:unit3\"" {  } { { "part4.vhd" "unit3" { Text "E:/VHDL/实验2/part4/part4.vhd" 37 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "display part4.vhd(221) " "Warning (10631): VHDL Process Statement warning at part4.vhd(221): inferring latch(es) for signal or variable \"display\", which holds its previous value in one or more paths through the process" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display\[0\] part4.vhd(221) " "Info (10041): Verilog HDL or VHDL info at part4.vhd(221): inferred latch for \"display\[0\]\"" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display\[1\] part4.vhd(221) " "Info (10041): Verilog HDL or VHDL info at part4.vhd(221): inferred latch for \"display\[1\]\"" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}