part4.tan.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "ITDB_TH_RESULT" "segment7:unit3\|display\[0\] SW\[4\] SW\[0\] 4.789 ns register " "Info: th for register \"segment7:unit3\|display\[0\]\" (data pin = \"SW\[4\]\", clock pin = \"SW\[0\]\") is 4.789 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW\[0\] destination 8.167 ns + Longest register " "Info: + Longest clock path from clock \"SW\[0\]\" to destination register is 8.167 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns SW\[0\] 1 CLK PIN_N25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N25; Fanout = 2; CLK Node = 'SW\[0\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.002 ns) + CELL(0.419 ns) 3.420 ns four_bit_adder:add_4bitof2\|f_adder:u1\|co~40 2 COMB LCCOMB_X32_Y1_N24 2 " "Info: 2: + IC(2.002 ns) + CELL(0.419 ns) = 3.420 ns; Loc. = LCCOMB_X32_Y1_N24; Fanout = 2; COMB Node = 'four_bit_adder:add_4bitof2\|f_adder:u1\|co~40'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.421 ns" { SW[0] four_bit_adder:add_4bitof2|f_adder:u1|co~40 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.255 ns) + CELL(0.271 ns) 3.946 ns four_bit_adder:add_4bitof2\|f_adder:u2\|co~74 3 COMB LCCOMB_X32_Y1_N30 2 " "Info: 3: + IC(0.255 ns) + CELL(0.271 ns) = 3.946 ns; Loc. = LCCOMB_X32_Y1_N30; Fanout = 2; COMB Node = 'four_bit_adder:add_4bitof2\|f_adder:u2\|co~74'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.526 ns" { four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.425 ns) + CELL(0.271 ns) 4.642 ns four_bit_adder:add_4bitof2\|f_adder:u3\|co~123 4 COMB LCCOMB_X33_Y1_N10 3 " "Info: 4: + IC(0.425 ns) + CELL(0.271 ns) = 4.642 ns; Loc. = LCCOMB_X33_Y1_N10; Fanout = 3; COMB Node = 'four_bit_adder:add_4bitof2\|f_adder:u3\|co~123'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.696 ns" { four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.150 ns) 5.051 ns four_bit_adder:add_4bitof2\|f_adder:u4\|co~10 5 COMB LCCOMB_X33_Y1_N26 5 " "Info: 5: + IC(0.259 ns) + CELL(0.150 ns) = 5.051 ns; Loc. = LCCOMB_X33_Y1_N26; Fanout = 5; COMB Node = 'four_bit_adder:add_4bitof2\|f_adder:u4\|co~10'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.409 ns" { four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.255 ns) + CELL(0.150 ns) 5.456 ns part2:unit1\|mux21:u4\|y~66 6 COMB LCCOMB_X33_Y1_N16 8 " "Info: 6: + IC(0.255 ns) + CELL(0.150 ns) = 5.456 ns; Loc. = LCCOMB_X33_Y1_N16; Fanout = 8; COMB Node = 'part2:unit1\|mux21:u4\|y~66'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.405 ns" { four_bit_adder:add_4bitof2|f_adder:u4|co~10 part2:unit1|mux21:u4|y~66 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.258 ns) + CELL(0.275 ns) 5.989 ns segment7:unit3\|Mux7~17 7 COMB LCCOMB_X33_Y1_N18 1 " "Info: 7: + IC(0.258 ns) + CELL(0.275 ns) = 5.989 ns; Loc. = LCCOMB_X33_Y1_N18; Fanout = 1; COMB Node = 'segment7:unit3\|Mux7~17'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.533 ns" { part2:unit1|mux21:u4|y~66 segment7:unit3|Mux7~17 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.000 ns) 6.690 ns segment7:unit3\|Mux7~17clkctrl 8 COMB CLKCTRL_G15 7 " "Info: 8: + IC(0.701 ns) + CELL(0.000 ns) = 6.690 ns; Loc. = CLKCTRL_G15; Fanout = 7; COMB Node = 'segment7:unit3\|Mux7~17clkctrl'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.701 ns" { segment7:unit3|Mux7~17 segment7:unit3|Mux7~17clkctrl } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.327 ns) + CELL(0.150 ns) 8.167 ns segment7:unit3\|display\[0\] 9 REG LCCOMB_X33_Y1_N24 1 " "Info: 9: + IC(1.327 ns) + CELL(0.150 ns) = 8.167 ns; Loc. = LCCOMB_X33_Y1_N24; Fanout = 1; REG Node = 'segment7:unit3\|display\[0\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.477 ns" { segment7:unit3|Mux7~17clkctrl segment7:unit3|display[0] } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.685 ns ( 32.88 % ) " "Info: Total cell delay = 2.685 ns ( 32.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.482 ns ( 67.12 % ) " "Info: Total interconnect delay = 5.482 ns ( 67.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "8.167 ns" { SW[0] four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 part2:unit1|mux21:u4|y~66 segment7:unit3|Mux7~17 segment7:unit3|Mux7~17clkctrl segment7:unit3|display[0] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "8.167 ns" { SW[0] SW[0]~combout four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 part2:unit1|mux21:u4|y~66 segment7:unit3|Mux7~17 segment7:unit3|Mux7~17clkctrl segment7:unit3|display[0] } { 0.000ns 0.000ns 2.002ns 0.255ns 0.425ns 0.259ns 0.255ns 0.258ns 0.701ns 1.327ns } { 0.000ns 0.999ns 0.419ns 0.271ns 0.271ns 0.150ns 0.150ns 0.275ns 0.000ns 0.150ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.378 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.378 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns SW\[4\] 1 CLK PIN_AF14 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AF14; Fanout = 2; CLK Node = 'SW\[4\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { SW[4] } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.771 ns) + CELL(0.275 ns) 2.045 ns four_bit_adder:add_4bitof2\|f_adder:u1\|so 2 COMB LCCOMB_X32_Y1_N18 7 " "Info: 2: + IC(0.771 ns) + CELL(0.275 ns) = 2.045 ns; Loc. = LCCOMB_X32_Y1_N18; Fanout = 7; COMB Node = 'four_bit_adder:add_4bitof2\|f_adder:u1\|so'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.046 ns" { SW[4] four_bit_adder:add_4bitof2|f_adder:u1|so } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.511 ns) + CELL(0.150 ns) 2.706 ns segment7:unit3\|Mux0~27 3 COMB LCCOMB_X33_Y1_N30 1 " "Info: 3: + IC(0.511 ns) + CELL(0.150 ns) = 2.706 ns; Loc. = LCCOMB_X33_Y1_N30; Fanout = 1; COMB Node = 'segment7:unit3\|Mux0~27'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.661 ns" { four_bit_adder:add_4bitof2|f_adder:u1|so segment7:unit3|Mux0~27 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.253 ns) + CELL(0.419 ns) 3.378 ns segment7:unit3\|display\[0\] 4 REG LCCOMB_X33_Y1_N24 1 " "Info: 4: + IC(0.253 ns) + CELL(0.419 ns) = 3.378 ns; Loc. = LCCOMB_X33_Y1_N24; Fanout = 1; REG Node = 'segment7:unit3\|display\[0\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.672 ns" { segment7:unit3|Mux0~27 segment7:unit3|display[0] } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.843 ns ( 54.56 % ) " "Info: Total cell delay = 1.843 ns ( 54.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.535 ns ( 45.44 % ) " "Info: Total interconnect delay = 1.535 ns ( 45.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.378 ns" { SW[4] four_bit_adder:add_4bitof2|f_adder:u1|so segment7:unit3|Mux0~27 segment7:unit3|display[0] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "3.378 ns" { SW[4] SW[4]~combout four_bit_adder:add_4bitof2|f_adder:u1|so segment7:unit3|Mux0~27 segment7:unit3|display[0] } { 0.000ns 0.000ns 0.771ns 0.511ns 0.253ns } { 0.000ns 0.999ns 0.275ns 0.150ns 0.419ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "8.167 ns" { SW[0] four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 part2:unit1|mux21:u4|y~66 segment7:unit3|Mux7~17 segment7:unit3|Mux7~17clkctrl segment7:unit3|display[0] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "8.167 ns" { SW[0] SW[0]~combout four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 part2:unit1|mux21:u4|y~66 segment7:unit3|Mux7~17 segment7:unit3|Mux7~17clkctrl segment7:unit3|display[0] } { 0.000ns 0.000ns 2.002ns 0.255ns 0.425ns 0.259ns 0.255ns 0.258ns 0.701ns 1.327ns } { 0.000ns 0.999ns 0.419ns 0.271ns 0.271ns 0.150ns 0.150ns 0.275ns 0.000ns 0.150ns } } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.378 ns" { SW[4] four_bit_adder:add_4bitof2|f_adder:u1|so segment7:unit3|Mux0~27 segment7:unit3|display[0] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "3.378 ns" { SW[4] SW[4]~combout four_bit_adder:add_4bitof2|f_adder:u1|so segment7:unit3|Mux0~27 segment7:unit3|display[0] } { 0.000ns 0.000ns 0.771ns 0.511ns 0.253ns } { 0.000ns 0.999ns 0.275ns 0.150ns 0.419ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 10 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 03 09:49:15 2007 " "Info: Processing ended: Sun Jun 03 09:49:15 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}