part4.tan.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "ITDB_TSU_RESULT" "segment7:unit3\|display\[1\] SW\[0\] SW\[3\] 3.864 ns register " "Info: tsu for register \"segment7:unit3\|display\[1\]\" (data pin = \"SW\[0\]\", clock pin = \"SW\[3\]\") is 3.864 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.897 ns + Longest pin register " "Info: + Longest pin to register delay is 7.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns SW\[0\] 1 CLK PIN_N25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N25; Fanout = 2; CLK Node = 'SW\[0\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.002 ns) + CELL(0.419 ns) 3.420 ns four_bit_adder:add_4bitof2\|f_adder:u1\|co~40 2 COMB LCCOMB_X32_Y1_N24 2 " "Info: 2: + IC(2.002 ns) + CELL(0.419 ns) = 3.420 ns; Loc. = LCCOMB_X32_Y1_N24; Fanout = 2; COMB Node = 'four_bit_adder:add_4bitof2\|f_adder:u1\|co~40'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.421 ns" { SW[0] four_bit_adder:add_4bitof2|f_adder:u1|co~40 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.255 ns) + CELL(0.271 ns) 3.946 ns four_bit_adder:add_4bitof2\|f_adder:u2\|co~74 3 COMB LCCOMB_X32_Y1_N30 2 " "Info: 3: + IC(0.255 ns) + CELL(0.271 ns) = 3.946 ns; Loc. = LCCOMB_X32_Y1_N30; Fanout = 2; COMB Node = 'four_bit_adder:add_4bitof2\|f_adder:u2\|co~74'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.526 ns" { four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.425 ns) + CELL(0.271 ns) 4.642 ns four_bit_adder:add_4bitof2\|f_adder:u3\|co~123 4 COMB LCCOMB_X33_Y1_N10 3 " "Info: 4: + IC(0.425 ns) + CELL(0.271 ns) = 4.642 ns; Loc. = LCCOMB_X33_Y1_N10; Fanout = 3; COMB Node = 'four_bit_adder:add_4bitof2\|f_adder:u3\|co~123'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.696 ns" { four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.150 ns) 5.051 ns four_bit_adder:add_4bitof2\|f_adder:u4\|co~10 5 COMB LCCOMB_X33_Y1_N26 5 " "Info: 5: + IC(0.259 ns) + CELL(0.150 ns) = 5.051 ns; Loc. = LCCOMB_X33_Y1_N26; Fanout = 5; COMB Node = 'four_bit_adder:add_4bitof2\|f_adder:u4\|co~10'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.409 ns" { four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.255 ns) + CELL(0.150 ns) 5.456 ns part2:unit1\|mux21:u4\|y~66 6 COMB LCCOMB_X33_Y1_N16 8 " "Info: 6: + IC(0.255 ns) + CELL(0.150 ns) = 5.456 ns; Loc. = LCCOMB_X33_Y1_N16; Fanout = 8; COMB Node = 'part2:unit1\|mux21:u4\|y~66'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.405 ns" { four_bit_adder:add_4bitof2|f_adder:u4|co~10 part2:unit1|mux21:u4|y~66 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.794 ns) + CELL(0.275 ns) 6.525 ns segment7:unit3\|Mux1~28 7 COMB LCCOMB_X33_Y1_N20 1 " "Info: 7: + IC(0.794 ns) + CELL(0.275 ns) = 6.525 ns; Loc. = LCCOMB_X33_Y1_N20; Fanout = 1; COMB Node = 'segment7:unit3\|Mux1~28'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.069 ns" { part2:unit1|mux21:u4|y~66 segment7:unit3|Mux1~28 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.953 ns) + CELL(0.419 ns) 7.897 ns segment7:unit3\|display\[1\] 8 REG LCCOMB_X25_Y1_N8 1 " "Info: 8: + IC(0.953 ns) + CELL(0.419 ns) = 7.897 ns; Loc. = LCCOMB_X25_Y1_N8; Fanout = 1; REG Node = 'segment7:unit3\|display\[1\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.372 ns" { segment7:unit3|Mux1~28 segment7:unit3|display[1] } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.954 ns ( 37.41 % ) " "Info: Total cell delay = 2.954 ns ( 37.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.943 ns ( 62.59 % ) " "Info: Total interconnect delay = 4.943 ns ( 62.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "7.897 ns" { SW[0] four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 part2:unit1|mux21:u4|y~66 segment7:unit3|Mux1~28 segment7:unit3|display[1] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "7.897 ns" { SW[0] SW[0]~combout four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 part2:unit1|mux21:u4|y~66 segment7:unit3|Mux1~28 segment7:unit3|display[1] } { 0.000ns 0.000ns 2.002ns 0.255ns 0.425ns 0.259ns 0.255ns 0.794ns 0.953ns } { 0.000ns 0.999ns 0.419ns 0.271ns 0.271ns 0.150ns 0.150ns 0.275ns 0.419ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.676 ns + " "Info: + Micro setup delay of destination is 0.676 ns" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW\[3\] destination 4.709 ns - Shortest register " "Info: - Shortest clock path from clock \"SW\[3\]\" to destination register is 4.709 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns SW\[3\] 1 CLK PIN_AE14 3 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AE14; Fanout = 3; CLK Node = 'SW\[3\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.668 ns) + CELL(0.438 ns) 2.105 ns part2:unit1\|mux21:u5\|y~13 2 COMB LCCOMB_X33_Y1_N28 8 " "Info: 2: + IC(0.668 ns) + CELL(0.438 ns) = 2.105 ns; Loc. = LCCOMB_X33_Y1_N28; Fanout = 8; COMB Node = 'part2:unit1\|mux21:u5\|y~13'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.106 ns" { SW[3] part2:unit1|mux21:u5|y~13 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.150 ns) 2.509 ns segment7:unit3\|Mux7~17 3 COMB LCCOMB_X33_Y1_N18 1 " "Info: 3: + IC(0.254 ns) + CELL(0.150 ns) = 2.509 ns; Loc. = LCCOMB_X33_Y1_N18; Fanout = 1; COMB Node = 'segment7:unit3\|Mux7~17'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.404 ns" { part2:unit1|mux21:u5|y~13 segment7:unit3|Mux7~17 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.000 ns) 3.210 ns segment7:unit3\|Mux7~17clkctrl 4 COMB CLKCTRL_G15 7 " "Info: 4: + IC(0.701 ns) + CELL(0.000 ns) = 3.210 ns; Loc. = CLKCTRL_G15; Fanout = 7; COMB Node = 'segment7:unit3\|Mux7~17clkctrl'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.701 ns" { segment7:unit3|Mux7~17 segment7:unit3|Mux7~17clkctrl } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.349 ns) + CELL(0.150 ns) 4.709 ns segment7:unit3\|display\[1\] 5 REG LCCOMB_X25_Y1_N8 1 " "Info: 5: + IC(1.349 ns) + CELL(0.150 ns) = 4.709 ns; Loc. = LCCOMB_X25_Y1_N8; Fanout = 1; REG Node = 'segment7:unit3\|display\[1\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.499 ns" { segment7:unit3|Mux7~17clkctrl segment7:unit3|display[1] } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.737 ns ( 36.89 % ) " "Info: Total cell delay = 1.737 ns ( 36.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.972 ns ( 63.11 % ) " "Info: Total interconnect delay = 2.972 ns ( 63.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "4.709 ns" { SW[3] part2:unit1|mux21:u5|y~13 segment7:unit3|Mux7~17 segment7:unit3|Mux7~17clkctrl segment7:unit3|display[1] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "4.709 ns" { SW[3] SW[3]~combout part2:unit1|mux21:u5|y~13 segment7:unit3|Mux7~17 segment7:unit3|Mux7~17clkctrl segment7:unit3|display[1] } { 0.000ns 0.000ns 0.668ns 0.254ns 0.701ns 1.349ns } { 0.000ns 0.999ns 0.438ns 0.150ns 0.000ns 0.150ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "7.897 ns" { SW[0] four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 part2:unit1|mux21:u4|y~66 segment7:unit3|Mux1~28 segment7:unit3|display[1] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "7.897 ns" { SW[0] SW[0]~combout four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 part2:unit1|mux21:u4|y~66 segment7:unit3|Mux1~28 segment7:unit3|display[1] } { 0.000ns 0.000ns 2.002ns 0.255ns 0.425ns 0.259ns 0.255ns 0.794ns 0.953ns } { 0.000ns 0.999ns 0.419ns 0.271ns 0.271ns 0.150ns 0.150ns 0.275ns 0.419ns } } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "4.709 ns" { SW[3] part2:unit1|mux21:u5|y~13 segment7:unit3|Mux7~17 segment7:unit3|Mux7~17clkctrl segment7:unit3|display[1] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "4.709 ns" { SW[3] SW[3]~combout part2:unit1|mux21:u5|y~13 segment7:unit3|Mux7~17 segment7:unit3|Mux7~17clkctrl segment7:unit3|display[1] } { 0.000ns 0.000ns 0.668ns 0.254ns 0.701ns 1.349ns } { 0.000ns 0.999ns 0.438ns 0.150ns 0.000ns 0.150ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "SW\[0\] HEX0\[0\] segment7:unit3\|display\[0\] 12.058 ns register " "Info: tco from clock \"SW\[0\]\" to destination pin \"HEX0\[0\]\" through register \"segment7:unit3\|display\[0\]\" is 12.058 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW\[0\] source 8.167 ns + Longest register " "Info: + Longest clock path from clock \"SW\[0\]\" to source register is 8.167 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns SW\[0\] 1 CLK PIN_N25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N25; Fanout = 2; CLK Node = 'SW\[0\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.002 ns) + CELL(0.419 ns) 3.420 ns four_bit_adder:add_4bitof2\|f_adder:u1\|co~40 2 COMB LCCOMB_X32_Y1_N24 2 " "Info: 2: + IC(2.002 ns) + CELL(0.419 ns) = 3.420 ns; Loc. = LCCOMB_X32_Y1_N24; Fanout = 2; COMB Node = 'four_bit_adder:add_4bitof2\|f_adder:u1\|co~40'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.421 ns" { SW[0] four_bit_adder:add_4bitof2|f_adder:u1|co~40 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.255 ns) + CELL(0.271 ns) 3.946 ns four_bit_adder:add_4bitof2\|f_adder:u2\|co~74 3 COMB LCCOMB_X32_Y1_N30 2 " "Info: 3: + IC(0.255 ns) + CELL(0.271 ns) = 3.946 ns; Loc. = LCCOMB_X32_Y1_N30; Fanout = 2; COMB Node = 'four_bit_adder:add_4bitof2\|f_adder:u2\|co~74'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.526 ns" { four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.425 ns) + CELL(0.271 ns) 4.642 ns four_bit_adder:add_4bitof2\|f_adder:u3\|co~123 4 COMB LCCOMB_X33_Y1_N10 3 " "Info: 4: + IC(0.425 ns) + CELL(0.271 ns) = 4.642 ns; Loc. = LCCOMB_X33_Y1_N10; Fanout = 3; COMB Node = 'four_bit_adder:add_4bitof2\|f_adder:u3\|co~123'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.696 ns" { four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.150 ns) 5.051 ns four_bit_adder:add_4bitof2\|f_adder:u4\|co~10 5 COMB LCCOMB_X33_Y1_N26 5 " "Info: 5: + IC(0.259 ns) + CELL(0.150 ns) = 5.051 ns; Loc. = LCCOMB_X33_Y1_N26; Fanout = 5; COMB Node = 'four_bit_adder:add_4bitof2\|f_adder:u4\|co~10'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.409 ns" { four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.255 ns) + CELL(0.150 ns) 5.456 ns part2:unit1\|mux21:u4\|y~66 6 COMB LCCOMB_X33_Y1_N16 8 " "Info: 6: + IC(0.255 ns) + CELL(0.150 ns) = 5.456 ns; Loc. = LCCOMB_X33_Y1_N16; Fanout = 8; COMB Node = 'part2:unit1\|mux21:u4\|y~66'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.405 ns" { four_bit_adder:add_4bitof2|f_adder:u4|co~10 part2:unit1|mux21:u4|y~66 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.258 ns) + CELL(0.275 ns) 5.989 ns segment7:unit3\|Mux7~17 7 COMB LCCOMB_X33_Y1_N18 1 " "Info: 7: + IC(0.258 ns) + CELL(0.275 ns) = 5.989 ns; Loc. = LCCOMB_X33_Y1_N18; Fanout = 1; COMB Node = 'segment7:unit3\|Mux7~17'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.533 ns" { part2:unit1|mux21:u4|y~66 segment7:unit3|Mux7~17 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.000 ns) 6.690 ns segment7:unit3\|Mux7~17clkctrl 8 COMB CLKCTRL_G15 7 " "Info: 8: + IC(0.701 ns) + CELL(0.000 ns) = 6.690 ns; Loc. = CLKCTRL_G15; Fanout = 7; COMB Node = 'segment7:unit3\|Mux7~17clkctrl'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.701 ns" { segment7:unit3|Mux7~17 segment7:unit3|Mux7~17clkctrl } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.327 ns) + CELL(0.150 ns) 8.167 ns segment7:unit3\|display\[0\] 9 REG LCCOMB_X33_Y1_N24 1 " "Info: 9: + IC(1.327 ns) + CELL(0.150 ns) = 8.167 ns; Loc. = LCCOMB_X33_Y1_N24; Fanout = 1; REG Node = 'segment7:unit3\|display\[0\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.477 ns" { segment7:unit3|Mux7~17clkctrl segment7:unit3|display[0] } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.685 ns ( 32.88 % ) " "Info: Total cell delay = 2.685 ns ( 32.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.482 ns ( 67.12 % ) " "Info: Total interconnect delay = 5.482 ns ( 67.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "8.167 ns" { SW[0] four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 part2:unit1|mux21:u4|y~66 segment7:unit3|Mux7~17 segment7:unit3|Mux7~17clkctrl segment7:unit3|display[0] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "8.167 ns" { SW[0] SW[0]~combout four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 part2:unit1|mux21:u4|y~66 segment7:unit3|Mux7~17 segment7:unit3|Mux7~17clkctrl segment7:unit3|display[0] } { 0.000ns 0.000ns 2.002ns 0.255ns 0.425ns 0.259ns 0.255ns 0.258ns 0.701ns 1.327ns } { 0.000ns 0.999ns 0.419ns 0.271ns 0.271ns 0.150ns 0.150ns 0.275ns 0.000ns 0.150ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.891 ns + Longest register pin " "Info: + Longest register to pin delay is 3.891 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns segment7:unit3\|display\[0\] 1 REG LCCOMB_X33_Y1_N24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X33_Y1_N24; Fanout = 1; REG Node = 'segment7:unit3\|display\[0\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { segment7:unit3|display[0] } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.093 ns) + CELL(2.798 ns) 3.891 ns HEX0\[0\] 2 PIN PIN_AF10 0 " "Info: 2: + IC(1.093 ns) + CELL(2.798 ns) = 3.891 ns; Loc. = PIN_AF10; Fanout = 0; PIN Node = 'HEX0\[0\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.891 ns" { segment7:unit3|display[0] HEX0[0] } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.798 ns ( 71.91 % ) " "Info: Total cell delay = 2.798 ns ( 71.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.093 ns ( 28.09 % ) " "Info: Total interconnect delay = 1.093 ns ( 28.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.891 ns" { segment7:unit3|display[0] HEX0[0] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "3.891 ns" { segment7:unit3|display[0] HEX0[0] } { 0.000ns 1.093ns } { 0.000ns 2.798ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "8.167 ns" { SW[0] four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 part2:unit1|mux21:u4|y~66 segment7:unit3|Mux7~17 segment7:unit3|Mux7~17clkctrl segment7:unit3|display[0] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "8.167 ns" { SW[0] SW[0]~combout four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 part2:unit1|mux21:u4|y~66 segment7:unit3|Mux7~17 segment7:unit3|Mux7~17clkctrl segment7:unit3|display[0] } { 0.000ns 0.000ns 2.002ns 0.255ns 0.425ns 0.259ns 0.255ns 0.258ns 0.701ns 1.327ns } { 0.000ns 0.999ns 0.419ns 0.271ns 0.271ns 0.150ns 0.150ns 0.275ns 0.000ns 0.150ns } } } { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.891 ns" { segment7:unit3|display[0] HEX0[0] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "3.891 ns" { segment7:unit3|display[0] HEX0[0] } { 0.000ns 1.093ns } { 0.000ns 2.798ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SW\[0\] HEX1\[1\] 10.435 ns Longest " "Info: Longest tpd from source pin \"SW\[0\]\" to destination pin \"HEX1\[1\]\" is 10.435 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns SW\[0\] 1 CLK PIN_N25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N25; Fanout = 2; CLK Node = 'SW\[0\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.002 ns) + CELL(0.419 ns) 3.420 ns four_bit_adder:add_4bitof2\|f_adder:u1\|co~40 2 COMB LCCOMB_X32_Y1_N24 2 " "Info: 2: + IC(2.002 ns) + CELL(0.419 ns) = 3.420 ns; Loc. = LCCOMB_X32_Y1_N24; Fanout = 2; COMB Node = 'four_bit_adder:add_4bitof2\|f_adder:u1\|co~40'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.421 ns" { SW[0] four_bit_adder:add_4bitof2|f_adder:u1|co~40 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.255 ns) + CELL(0.271 ns) 3.946 ns four_bit_adder:add_4bitof2\|f_adder:u2\|co~74 3 COMB LCCOMB_X32_Y1_N30 2 " "Info: 3: + IC(0.255 ns) + CELL(0.271 ns) = 3.946 ns; Loc. = LCCOMB_X32_Y1_N30; Fanout = 2; COMB Node = 'four_bit_adder:add_4bitof2\|f_adder:u2\|co~74'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.526 ns" { four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.425 ns) + CELL(0.271 ns) 4.642 ns four_bit_adder:add_4bitof2\|f_adder:u3\|co~123 4 COMB LCCOMB_X33_Y1_N10 3 " "Info: 4: + IC(0.425 ns) + CELL(0.271 ns) = 4.642 ns; Loc. = LCCOMB_X33_Y1_N10; Fanout = 3; COMB Node = 'four_bit_adder:add_4bitof2\|f_adder:u3\|co~123'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.696 ns" { four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.150 ns) 5.051 ns four_bit_adder:add_4bitof2\|f_adder:u4\|co~10 5 COMB LCCOMB_X33_Y1_N26 5 " "Info: 5: + IC(0.259 ns) + CELL(0.150 ns) = 5.051 ns; Loc. = LCCOMB_X33_Y1_N26; Fanout = 5; COMB Node = 'four_bit_adder:add_4bitof2\|f_adder:u4\|co~10'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.409 ns" { four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.595 ns) + CELL(2.789 ns) 10.435 ns HEX1\[1\] 6 PIN PIN_V21 0 " "Info: 6: + IC(2.595 ns) + CELL(2.789 ns) = 10.435 ns; Loc. = PIN_V21; Fanout = 0; PIN Node = 'HEX1\[1\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.384 ns" { four_bit_adder:add_4bitof2|f_adder:u4|co~10 HEX1[1] } "NODE_NAME" } } { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.899 ns ( 46.95 % ) " "Info: Total cell delay = 4.899 ns ( 46.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.536 ns ( 53.05 % ) " "Info: Total interconnect delay = 5.536 ns ( 53.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "10.435 ns" { SW[0] four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 HEX1[1] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "10.435 ns" { SW[0] SW[0]~combout four_bit_adder:add_4bitof2|f_adder:u1|co~40 four_bit_adder:add_4bitof2|f_adder:u2|co~74 four_bit_adder:add_4bitof2|f_adder:u3|co~123 four_bit_adder:add_4bitof2|f_adder:u4|co~10 HEX1[1] } { 0.000ns 0.000ns 2.002ns 0.255ns 0.425ns 0.259ns 2.595ns } { 0.000ns 0.999ns 0.419ns 0.271ns 0.271ns 0.150ns 2.789ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}